74HC4051PW-Q100 NXP Semiconductors, 74HC4051PW-Q100 Datasheet

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74HC4051PW-Q100

Manufacturer Part Number
74HC4051PW-Q100
Description
Encoders, Decoders, Multiplexers & Demultiplexers 8-ChanMux/Demux 10V
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74HC4051PW-Q100

Product
Multiplexers / Demultiplexers
Logic Family
74HC
Number Of Lines (input / Output)
8 / 8
Propagation Delay Time
90 ns
Supply Voltage - Max
10 V
Supply Voltage - Min
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-16
Minimum Operating Temperature
- 40 C
Number Of Input Lines
8
Number Of Output Lines
8
Operating Temperature Range
- 40 C to + 125 C
Operating Voltage
2 V to 10 V
Power Dissipation
500 mW
Part # Aliases
74HC4051PW-Q100,11
1. General description
2. Features and benefits
The 74HC4051-Q100; 74HCT4051-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL). The device is specified in compliance
with JEDEC standard no. 7A.
The 74HC4051-Q100; 74HCT4051-Q100 is an 8-channel analog
multiplexer/demultiplexer with three digital select inputs (S0 to S2), an active-LOW enable
input (E), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z).
With E LOW, one of the eight switches is selected (low impedance ON-state) by S0 to S2.
With E HIGH, all switches are in the high-impedance OFF-state, independent of S0 to S2.
V
The V
74HCT4051-Q100. The analog inputs/outputs (Y0 to Y7, and Z) can swing between V
as a positive limit and V
operation as a digital multiplexer/demultiplexer, V
ground).
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
CC
74HC4051-Q100; 74HCT4051-Q100
8-channel analog multiplexer/demultiplexer
Rev. 2 — 8 October 2012
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Wide analog input voltage range from 5 V to +5 V
Low ON resistance:
Logic level translation: to enable 5 V logic to communicate with 5 V analog signals
Typical ‘break before make’ built-in
ESD protection:
Multiple package options
and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).
CC
Specified from 40 C to +85 C and from 40 C to +125 C
80  (typical) at V
70  (typical) at V
60  (typical) at V
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
CDM AEC-Q100-011 revision B exceeds 1000 V
to GND ranges are 2.0 V to 10.0 V for 74HC4051-Q100 and 4.5 V to 5.5 V for
EE
CC
CC
CC
as a negative limit. V
 V
 V
 V
EE
EE
EE
= 4.5 V
= 6.0 V
= 9.0 V
CC
EE
 V
is connected to GND (typically
EE
may not exceed 10.0 V. For
Product data sheet
CC

Related parts for 74HC4051PW-Q100

74HC4051PW-Q100 Summary of contents

Page 1

Rev. 2 — 8 October 2012 1. General description The 74HC4051-Q100; 74HCT4051-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The device is specified in compliance with JEDEC ...

Page 2

... Signal gating 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74HC4051D-Q100 74HCT4051D-Q100 40 C to +125 C 74HC4051PW-Q100 74HCT4051PW-Q100 40 C to +125 C 74HC4051BQ-Q100 74HCT4051BQ-Q100 74HC_HCT4051_Q100 Product data sheet 74HC4051-Q100; 74HCT4051-Q100 8-channel analog multiplexer/demultiplexer Description SO16 plastic small outline package ...

Page 3

... NXP Semiconductors 5. Functional diagram Fig 1. Functional diagram 74HC_HCT4051_Q100 Product data sheet 74HC4051-Q100; 74HCT4051-Q100 LOGIC 1-OF-8 LEVEL DECODER CONVERSION GND V EE All information provided in this document is subject to legal disclaimers. Rev. 2 — 8 October 2012 8-channel analog multiplexer/demultiplexer 13 Y0 ...

Page 4

... NXP Semiconductors Fig 2. Logic symbol from logic Fig 4. Schematic diagram (one switch) 74HC_HCT4051_Q100 Product data sheet 74HC4051-Q100; 74HCT4051-Q100 001aad541 Fig 3. All information provided in this document is subject to legal disclaimers. ...

Page 5

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74HC4051-Q100 74HCT4051-Q100 GND Fig 5. Pin configuration SO16 and TSSOP16 6.2 Pin description Table 2. Pin description Symbol Pin GND 8 S0, S1, S2 11, 10, 9 Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12 independent input or output ...

Page 6

... NXP Semiconductors 7. Functional description 7.1 Function table [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V ...

Page 7

... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb t/V input transition rise and fall rate 10 V GND CC ( operating area Fig 7. ...

Page 8

... NXP Semiconductors 10. Static characteristics Table 6. R resistance per switch for 74HC4051-Q100 and 74HCT4051-Q100 for test circuit see the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. ...

Page 9

... NXP Semiconductors Table 6. R resistance per switch for 74HC4051-Q100 and 74HCT4051-Q100 for test circuit see the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os  ...

Page 10

... NXP Semiconductors V sw from select Sn input Yn GND V is  -------- - Fig 9. Test circuit for measuring R Table 7. Static characteristics for 74HC4051-Q100 Voltages are referenced to GND (ground = 0 V the input voltage at pins whichever is assigned as an input. ...

Page 11

... NXP Semiconductors Table 7. Static characteristics for 74HC4051-Q100 Voltages are referenced to GND (ground = 0 V the input voltage at pins whichever is assigned as an input the output voltage at pins Z or Yn, whichever is assigned as an output. os Symbol Parameter I supply current CC C input capacitance I C switch capacitance sw =  ...

Page 12

... NXP Semiconductors Table 7. Static characteristics for 74HC4051-Q100 Voltages are referenced to GND (ground = 0 V the input voltage at pins whichever is assigned as an input the output voltage at pins Z or Yn, whichever is assigned as an output. os Symbol Parameter I input leakage current I I OFF-state leakage ...

Page 13

... NXP Semiconductors Table 8. Static characteristics for 74HCT4051-Q100 Voltages are referenced to GND (ground = 0 V the input voltage at pins whichever is assigned as an input the output voltage at pins Z or Yn, whichever is assigned as an output. os Symbol Parameter = 40 C to +85 C T amb V HIGH-level input ...

Page 14

... NXP Semiconductors and and Fig 11. Test circuit for measuring OFF-state current and V = open-circuit and V = open-circuit Fig 12. Test circuit for measuring ON-state current 11. Dynamic characteristics Table 9. Dynamic characteristics for 74HC4051-Q100 GND = 0 V ...

Page 15

... NXP Semiconductors Table 9. Dynamic characteristics for 74HC4051-Q100 GND = ns pF; for test circuit see the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter ...

Page 16

... NXP Semiconductors Table 9. Dynamic characteristics for 74HC4051-Q100 GND = ns pF; for test circuit see the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter ...

Page 17

... NXP Semiconductors Table 9. Dynamic characteristics for 74HC4051-Q100 GND = ns pF; for test circuit see the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter ...

Page 18

... NXP Semiconductors Table 10. Dynamic characteristics for 74HCT4051-Q100 GND = ns pF; for test circuit see the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter ...

Page 19

... NXP Semiconductors Table 10. Dynamic characteristics for 74HCT4051-Q100 GND = ns pF; for test circuit see the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter ...

Page 20

... NXP Semiconductors E, Sn inputs For 74HC4051-Q100 For 74HCT4051-Q100 Fig 14. Turn-on and turn-off times Definitions for test circuit; see R = termination resistance should be equal to the output impedance load capacitance including jig and probe capacitance load resistance Test selection switch. ...

Page 21

... NXP Semiconductors Table 11. Test data Test Input PHL PLH [ PZH PHZ [ PZL PLZ [ ns; when measuring max [2] V values For 74HC4051-Q100 For 74HCT4051-Q100 74HC_HCT4051_Q100 Product data sheet 74HC4051-Q100; 74HCT4051-Q100 ...

Page 22

... NXP Semiconductors 11.1 Additional dynamic characteristics Table 12. Additional dynamic characteristics Recommended conditions and typical values; GND = the input voltage at pins nYn or nZ, whichever is assigned as an input the output voltage at pins nYn or nZ, whichever is assigned as an output. os Symbol Parameter d sine-wave distortion sin  ...

Page 23

... NXP Semiconductors V = 4.5 V; GND = Test circuit 0 iso (dB 100 10 b. Isolation (OFF-state function of frequency Fig 17. Test circuit for measuring isolation (OFF-state) G Fig 18. Test circuit for measuring crosstalk between control input and any switch 74HC_HCT4051_Q100 Product data sheet 74HC4051-Q100 ...

Page 24

... NXP Semiconductors V = 4.5 V; GND = Test circuit (dB Typical frequency response Fig 19. Test circuit for frequency response 74HC_HCT4051_Q100 Product data sheet 74HC4051-Q100; 74HCT4051-Q100 Yn/Z Z/ GND EE = 4  k All information provided in this document is subject to legal disclaimers ...

Page 25

... NXP Semiconductors 12. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 26

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 27

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 28

... NXP Semiconductors 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic MIL Military 14. Revision history Table 14. Revision history Document ID Release date Data sheet status 74HC_HCT4051_Q100 v.2 20121008 • Modifications: 74HC_HCT4051_Q100 v.1 20120709 ...

Page 29

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 30

... NXP Semiconductors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations ...

Page 31

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 14 11 ...

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