DS26528GA4 Maxim Integrated, DS26528GA4 Datasheet - Page 127

• Manufacturer Part Number: DS26528GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GA4

• Part # Aliases: 90-26528-GA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 4: Receive SLC-96 Synchronizer Enable (RSLC96). See Section
Bits 3 and 2: Out of Frame Select Bits (OOF[2:1]).
Bit 1: Receive RAI Integration Enable (RAIIE). The ESF RAI indication can be interrupted for a period not to
exceed 100ms per interruption (T1.403). In ESF mode, setting RAIIE will cause the RAI status from the DS26528
to be integrated for 200ms.
Bit 0: Receive-Side D4 Remote Alarm Select (RD4RM).
OOF2
0
0
1
1
0 = SLC-96 synchronizer is disabled
1 = SLC-96 synchronizer is enabled
0 =
1 =
0 = zeros in bit 2 of all channels
1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode)
OOF1
0
1
0
1
—
7
0
RAI detects when 16 consecutive patterns of 00FF appear in the FDL.
RAI clears when 14 or fewer patterns of 00FF hex out of 16 possible appear in the FDL.
RAI detects when the condition has been present for greater than 200ms.
RAI clears when the condition has been absent for greater than 200ms.
OUT OF FRAME CRITERIA
2/4 frame bits in error
2/5 frame bits in error
2/6 frame bits in error
2/6 frame bits in error
T1RCR2 (T1 Mode)
Receive Control Register 2
014h + (200h x n): where n = 0 to 7, for Ports 1 to 8
—
6
0
—
5
0
RSLC96
127 of 276
4
0
OOF2
3
0
8.9.4.5
DS26528 Octal T1/E1/J1 Transceiver
for SLC-96 details.
OOF1
2
0
RAIIE
1
0
RD4RM
0
0