DS26528GA4 Maxim Integrated, DS26528GA4 Datasheet - Page 129

• Manufacturer Part Number: DS26528GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GA4

• Part # Aliases: 90-26528-GA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive BOC Reset (RBR). The host should set this bit to force a reset of the BOC circuitry. Note that this is
an acknowledged reset, that is, the host need only set the bit and the DS26528 will clear it once the reset operation
is complete (less than 250μs). Modifications to the RBF[1:0] and RBD[1:0] bits will not be applied to the BOC
controller until a BOC reset has been completed.
Note: This bit will clear automatically if RMMR.INIT_DONE has been set.
Bits 5 and 4: Receive BOC Disintegration Bits (RBD[1:0]). The BOC disintegration filter sets the number of
message bits that must be received without a valid BOC to set the BC bit indicating that a valid BOC is no longer
being received.
Bits 2 and 1: Receive BOC Filter Bits (RBF[1:0]). The BOC filter sets the number of consecutive patterns that
must be received without error prior to an indication of a valid message.
Note 1: The DS26528’s BOC controller does not integrate and disintegrate concurrently. Therefore, if the maximum integration
time and the maximum disintegration time are used together, BOC messages that repeat fewer than 11 times may not be
detected.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Per-Channel Idle Code Bits (C[7:0]). C0 is the LSB of the code (this bit is transmitted last). Address
020h is for channel 1. Address 037h is for channel 24. Address 03Fh is for channel 32. RIDR1:RIDR24 are T1
mode only. RIDR25:RIDR32 are E1 mode only.
RBD1
RBF1
0
0
1
1
0
0
1
1
RBR
C7
RBD0
7
0
RBF0
7
0
0
1
0
1
0
1
0
1
T1RBOCC (T1 Mode Only)
Receive BOC Control Register
015h + (200h x n): where n = 0 to 7, for Ports 1 to 8
RIDR1 to RIDR32
Receive Idle Code Definition Registers 1 to 32
020h to 03Fh + (200h x n): where n = 0 to 7, for Ports 1 to 8
VALID SEQUENCE IDENTIFICATION
FOR BOC CLEAR IDENTIFICATION
CONSECUTIVE BOC CODES FOR
C6
—
6
0
6
0
CONSECUTIVE MESSAGE BITS
64 (See Note 1)
7 (See Note 1)
RBD1
C5
5
0
5
0
None
16
32
48
3
5
129 of 276
RBD0
C4
4
0
4
0
C3
—
3
0
3
0
DS26528 Octal T1/E1/J1 Transceiver
RBF1
C2
2
0
2
0
RBF0
C1
1
0
1
0
C0
—
0
0
0
0