DS32506NW Maxim Integrated, DS32506NW Datasheet - Page 18

• Manufacturer Part Number: DS32506NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506NW

• Part # Aliases: 90-32506-NW0

Table 7-4. Global Pin Descriptions
IFSEL[2:0]
RESREF
NAME
TEST
RST
HW
HIZ
TYPE
Ipd
Ipu
Oa
I
I
I
Microprocessor Interface Select. When no microprocessor interface is selected, all
microprocessor interface inputs are ignored and internally pulled low, and all microprocessor
interface outputs are put in a high-impedance state. See Section
000 = no microprocessor interface (must set
001 = reserved
010 = SPI serial interface, address and data MSB first
011 = SPI serial interface, address and data LSB first
100 = 8-bit parallel interface, Intel style (CS, RD,
101 = 8-bit parallel interface, Motorola style (CS,
110 = 16-bit parallel interface, Intel style (CS, RD,
111 = 16- bit parallel interface, Motorola style (CS,
Hardware Interface Enable. When the hardware interface pins are disabled, all hardware
control inputs are ignored and internally pulled low, and all hardware status outputs are put in a
high impedance state. See Section
0 = Hardware interface pins disabled
1 = Hardware interface pins enabled
Factory Test Enable (Active Low). This pin enables the internal scan test mode when low.
For normal operation tie high. This is an asynchronous input.
High-Impedance Test Enable (Active Low). This signal is used to enable testing. When this
signal is low while
high-impedance state. For normal operation this signal is high. This is an asynchronous input.
Reset (Active Low, Open Drain). When this global asynchronous reset is pulled low, all
internal circuitry is reset and all internal registers are forced to their default values. The device
is held in reset as long as
cycles. See Section 8.11.
Reference Resistor. This pin is tied to VSS through a 10kΩ ±1% resistor. This accurate
resistor is used to calibrate on-chip resistor values including internal transmit and receive
termination resistors.
JTRST
is low, all the digital output and bidirectional pins are placed in the
RST
18 of 130
is low.
6
for details.
RST
FUNCTION
should be held low for at least two reference clock
HW
WR
R/W
= 1 and use hardware interface)
WR
R/W
control signals)
,
control signals)
DS
,
DS
control signals)
control signals)
DS32506/DS32508/DS32512
6
for details.