DS32506NW Maxim Integrated, DS32506NW Datasheet - Page 26

• Manufacturer Part Number: DS32506NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506NW

• Part # Aliases: 90-32506-NW0

8.2.9 Driver Monitor and Output Failure Detection
The transmit driver monitor compares the amplitude of the transmit waveform to thresholds V
the amplitude is less than V
activates the
of LIU.SR:TDM can cause an interrupt if enabled by LIU.SRIE:TDMIE. When the transmitter is disabled, the
transmit driver monitor is also disabled. The transmit driver monitor is clocked by the LIU’s reference clock.
Note that the transmit driver monitor can be affected by reflections caused by shorts and opens on the line. A short
circuit at a distance less than a few inches (~11 inches for FR-4 material) can introduce inverted reflections that
reduce the outgoing pulse amplitude below the V
status bit. Similarly an open circuit a similar distance away can introduce noninverted reflections that increase the
outgoing amplitude above the V
and opens at larger distances away from
this effect is data-pattern dependent.
If either
declared by setting the LIU.SR:TFAIL status bit. A change of state of the TFAIL status bit can cause an interrupt if
enabled by LIU.SRIE:TFAILIE. TFAIL is cleared when activity is detected on both
8.2.10 Power-Down
To minimize power consumption when the transmitter is not being used, the
PORT.CR1:TPD configuration bit (per port) can be asserted. When the transmitter is powered down, the
TXN
8.2.11 Jitter Generation (Intrinsic)
The transmitter meets the jitter generation requirements of all applicable standards in
jitter attenuator enabled. Generated jitter is measured with a jitter-free, 0ppm input clock.
Table 8-1. Jitter Generation
8.2.12 Jitter Transfer
Without the jitter attenuator on the transmit side, the transmitter passes jitter through unchanged. With the jitter
attenuator enabled on the transmit side, the transmitter meets the jitter transfer requirements of all applicable
telecommunication standards in
SIGNAL STANDARD REQUIREMENT
STS-1
STS-1
DS3
DS3
DS3
E3
pins are put in a high-impedance state and the transmit drivers are powered down.
TXP
TDM
or
GR-499
GR-253
GR-253
T1.404
T1.404
G.751
TXN
output pin (if the hardware interface is enabled) and sets the LIU.SR:TDM status bit. The setting
is not connected (open), shorted to V
TXMIN
0.01 UI
0.05 UI
0.05 UI
0.10 UI
0.3 UI
0.5 UI
TXMAX
Table
or greater than V
RMS
P-P
RMS
threshold and thereby activate the
P-P
P-P
P-P
1-1. See
TXP/TXN
100Hz to 800kHz
30kHz to 400kHz
12kHz to 400kHz
12kHz to 400kHz
Figure
10Hz to 400kHz
10Hz to 400kHz
BANDWIDTH
TXMIN
26 of 130
can also activate the
TXMAX
threshold and thereby activate the
8-7.
for approximately 32 MCLK cycles, then the monitor
DD
, or shorted to V
WITHOUT CLAD
0.015
0.005
TYP
0.01
0.02
0.02
0.04
TDM
TDM
DS325xx JITTER
pin and/or the TDM status bit. Shorts
SS
0.025
0.008
MAX
pin and/or the TDM status bit, but
0.02
0.03
0.03
0.06
TXP
, then a transmit failure alarm is
DS32506/DS32508/DS32512
Table
TPD
and
0.007
WITH CLAD
TDM
TYP
0.01
0.05
0.04
0.04
0.06
TXN
8-1, with or without the
pin (all ports) or the
.
pin and/or the TDM
TXMIN
MAX
0.02
0.06
0.05
0.05
0.01
0.08
and V
TXP
UNITS
UI
UI
TXMAX
UI
UI
UI
UI
RMS
RMS
P-P
P-P
P-P
P-P
and
. If