DS32506NW Maxim Integrated, DS32506NW Datasheet - Page 81

• Manufacturer Part Number: DS32506NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32506NW

• Part # Aliases: 90-32506-NW0

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 3: Excessive Zero Count (EXZC). See Section 8.3.6.
Bit 1: Bipolar Violation Count (BPVC). See Section 8.3.6.
Bit 0: Loss of Signal (LOS). See Section
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 5: Zero Suppression Code Detect Latched (ZSCDL). This bit is set when a B3ZS or HDB3 signature is
detected. When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:ZSCDIE, PORT.ISRIE:LDSRIE
and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.3.6.
Bit 4: Excessive Zero Latched (EXZL). This bit is set when an excessive zero event is detected on the incoming
bipolar data stream. When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:EXZIE,
PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.3.6.
Bit 3: Excessive Zero Count Latched (EXZCL). This bit is set when LINE.RSR:EXZC transitions from zero to
one. When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:EXZCIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set. See Section 8.3.6.
Bit 2: Bipolar Violation Latched (BPVL). This bit is set when a bipolar violation (or E3 LCV if enabled) is detected
on the incoming bipolar data stream. When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:BPVIE,
PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.3.6.
Bit 1: Bipolar Violation Count Latched (BPVCL). This bit is set when LINE.RSR:BPVC transitions from zero to
one. When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:BPVCIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set. See Section 8.3.6.
Bit 0: Loss of Signal Change Latched (LOSL). This bit is set when LINE.RSR:LOS changes state. When set, this
bit causes an interrupt if interrupt enables LINE.RSRIE:LOSIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE
are all set. See Section
0 = the Receive Excessive Zero Count Register ( LINE.REXZCR ) is zero
1 = the Receive Excessive Zero Count Register ( LINE.REXZCR ) is one or more
0 = the Receive Bipolar Violation Count Register ( LINE.RBPVCR ) is zero
1 = the Receive Bipolar Violation Count Register ( LINE.RBPVCR ) is one or more
0 = receive line interface is not in a LOS condition
1 = receive line interface is in an LOS condition
15
15
—
—
—
—
0
7
0
0
7
0
8.3.5.
14
14
—
—
—
—
0
6
0
0
6
0
LINE.RSR
B3ZS/HDB3 Receive Status Register
n * 80h + 44h
LINE.RSRL
B3ZS/HDB3 Receive Status Register Latched
n * 80h + 46h
ZSCDL
13
—
—
13
—
0
5
0
0
5
0
8.3.5.
EXZL
81 of 130
12
—
—
12
—
0
4
0
0
4
0
EXZCL
EXZC
11
11
—
—
0
3
0
0
3
0
BPVL
10
10
—
—
—
0
2
0
0
2
0
DS32506/DS32508/DS32512
BPVCL
BPVC
—
—
9
0
1
0
9
0
1
0
LOSL
LOS
—
—
8
0
0
0
8
0
0
0