74AUP1G240GW-G NXP Semiconductors, 74AUP1G240GW-G Datasheet
74AUP1G240GW-G
Manufacturer Part Number
74AUP1G240GW-G
Description
Buffers & Line Drivers 3V SINGLE BUF/LD INV 3S
Manufacturer
NXP Semiconductors
Datasheet
1.74AUP1G240GW-G.pdf
(23 pages)
Specifications of 74AUP1G240GW-G
Product Category
Buffers & Line Drivers
Rohs
yes
Number Of Input Lines
1
Number Of Output Lines
1
Polarity
Inverting
Supply Voltage - Max
3.6 V
Supply Voltage - Min
0.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
UMT-5
High Level Output Current
- 4 mA
Logic Family
AUP
Logic Type
CMOS
Low Level Output Current
4 mA
Minimum Operating Temperature
- 40 C
Number Of Channels Per Chip
1
Output Type
3-State
Propagation Delay Time
21.6 ns at 1.1 V to 1.3 V, 12.3 ns at 1.4 V to 1.6 V, 9.5 ns at 1.65 V to 1.95 V, 7.1 ns at 2.3 V to 2.7 V, 6.4 ns at 3 V to 3.6 V
Factory Pack Quantity
3000
Part # Aliases
74AUP1G240GW,125
1. General description
2. Features and benefits
The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The
3-state output is controlled by the output enable input (OE). A HIGH level at pin OE
causes the output to assume a high-impedance OFF-state.
This device has the input-disable feature, which allows floating input signals. The inputs
are disabled when the output enable input OE is HIGH.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial Power-down applications using I
The I
the device when it is powered down.
CC
74AUP1G240
Low-power inverting buffer/line driver; 3-state
Rev. 4 — 29 June 2012
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
Input-disable feature allows floating input conditions
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
range from 0.8 V to 3.6 V.
OFF
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 A (maximum)
CC
Product data sheet
OFF
.
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