XRT83SL216ES Exar, XRT83SL216ES Datasheet - Page 17

• Manufacturer Part Number: XRT83SL216ES
• Description: Peripheral Drivers & Components - PCIs 16 CH E1 LIU SH
• Manufacturer: Exar

Specifications of XRT83SL216ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 1.0.0
The receive path consists of 16 independent E1 receivers. The following section describes the complete
receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified block diagram of the receive
path is shown in
In the receive path, the line signal is coupled into the RTIP and RRing pins via a 2:1 transformer and are
converted into digital pulses by an equalizer and an adaptive data slicer. Clock and data signals are recovered
from the output of the slicer with the help of a digital PLL that provides excellent jitter accommodation for high
input jitter tolerance.
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. In the absence of an
incoming signal, RCLK maintains its timing by using MCLK as its reference. The recovered data can be
updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To update data on
the falling edge of RCLK, set RCLKinv to "1" in the appropriate global register.
the receive data updated on the rising edge of RCLK.
on the falling edge of RCLK. The timing specifications are shown in
F
F
F
1.0 RECEIVE PATH LINE INTERFACE
1.1
1.2
IGURE
IGURE
IGURE
3. S
4. R
5. R
Peak Detector/Data Slicer
Clock and Data Recovery
IMPLIFIED
ECEIVE
ECEIVE
RNEG
RPOS
RCLK
Figure
D
D
ATA
ATA
B
LOCK
R P O S
R N E G
3.
R C LK
or
U
U
RPOS
RNEG
RCLK
PDATED ON THE
PDATED ON THE
Decoder
or
HDB3
D
IAGRAM OF THE
Attenuator
Rx Jitter
R
F
R
ALLING
ISING
D Y
R
DY
R
ECEIVE
E
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
DGE OF
E
Clock & Data
DGE OF
Figure 5
15
Recovery
P
ATH
R
R
O H
RCLK
OH
RCLK
L
R C LK
RCLK
INE
is a timing diagram of the receive data updated
F
R
T
ERMINATION
Table
Rx Equalizer &
Peak Detector
RCLK
R C LK
1.
R
F
Figure 4
(RTIP/RRING)
RTIP
RRING
is a timing diagram of
XRT83SL216