XRT83SL216ES Exar, XRT83SL216ES Datasheet - Page 22

• Manufacturer Part Number: XRT83SL216ES
• Description: Peripheral Drivers & Components - PCIs 16 CH E1 LIU SH
• Manufacturer: Exar

Specifications of XRT83SL216ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83SL216
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
N
In single rail mode, the LIU can encode the TPOS input signal to AMI or HDB3 data. If HDB3 encoding is
selected, any sequence with four or more consecutive zeros in the input will be replaced with 000V or B00V,
where "B" indicates a pulse conforming to the bipolar rule and "V" representing a pulse violating the rule. An
example of HDB3 encoding is shown in
The XRT83SL216 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed to E1 data, stuffing bits are typically removed
which can leave gaps in the incoming data stream. The JA can be configured in the transmit path with a 32-Bit
or 64-Bit FIFO that is used to smooth the gapped clock into a steady E1 output. The maximum gap width the
JA in the Transmit path can tolerate is shown in
N
2.2
2.3
OTE
OTE
TCLK Rise Time (10% to 90%)
TCLK Fall Time (90% to 10%)
Transmit Data Setup Time
Transmit Data Hold Time
: VDD=3.3V ±5%, T
: If the LIU is used in a loop timing system, the JA should be configured in the receive path. See the Receive Section
of this datasheet.
TCLK Duty Cycle
HDB3 Encoder
Transmit Jitter Attenuator
P
ARAMETER
HDB3 (Case 1)
HDB3 (Case 2)
T
ABLE
Input
A
=25°C, Unless Otherwise Specified
4: M
T
ABLE
AXIMUM
FIFO D
2: T
T
S
ABLE
32-Bit
64-Bit
TCLK
TCLK
T
YMBOL
IMING
T
T
CDU
G
HO
SU
Table
EPTH
AP
R
F
3: E
N
S
W
UMBER OF
PECIFICATIONS FOR
IDTH FOR
XAMPLES OF
3.
Table
N
EXT
Even
Odd
P
M
4 Z
20
30
50
30
4.
-
-
ULSES
M
IN
ULTIPLEXER
EROS
HDB3 E
B
M
EFORE
AXIMUM
TCLK/TPOS/TNEG
NCODING
/M
20 UI
50 UI
T
50
YP
APPER
-
-
-
-
G
AP
W
IDTH
A
PPLICATIONS
B00V
000V
0000
M
70
40
40
AX
-
-
U
REV. 1.0.0
NITS
ns
ns
ns
ns
%