XRT83SL216ES Exar, XRT83SL216ES Datasheet - Page 19

• Manufacturer Part Number: XRT83SL216ES
• Description: Peripheral Drivers & Components - PCIs 16 CH E1 LIU SH
• Manufacturer: Exar

Specifications of XRT83SL216ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 1.0.0
The XRT83SL216 supports both G.775 or ETSI-300-233 RLOS detection scheme.
In G.775 mode, RLOS is declared when the received signal is less than 320mV for more than 32 consecutive
pulse periods (typical). The device clears RLOS when the receive signal achieves 12.5% ones density with no
more than 15 consecutive zeros in a 32 bit sliding window and the signal level exceeds 550mV (typical).
In ETSI-300-233 mode the device declares RLOS when the input level drops below 320mV (typical) for more
than 2048 pulse periods (1msec). The device clears RLOS when the receive signal achieves 12.5% ones
density with no more than 15 consecutive zeros in a 32 bit sliding window and the signal level exceeds 550mV
(typical).
The XRT83SL216 adheres to ITU-T G.775 or ETSI-300-233 specifications for an all ones pattern detection by
programming the appropriate channel register. The alarm indication signal is set to "1" if an all ones pattern is
detected. In G.775 mode, AIS is defined as 2 or less zeros in 2 consecutive double frame (512-bit window)
periods. AIS will clear when the incoming signal has 3 or more zeros in the same time period. In ETSI-300-233
mode, AIS is defined as less than 3 zeros in a 512-bit window.
In HDB3 mode, the LCV pin will be set to "High" if the receiver detects excessive zero’s, bipolar violations or
HDB3 code violations. If the device is configured in AMI mode, any bipolar violations will cause the LCV pin to
go "High".
The jitter attenuator can be configured in the receive path to reduce phase and frequency jitter in the recovered
clock. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. If
the LIU is used for line synchronization (loop timing systems), the JA should be enabled. When the Read and
Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the jitter
attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this condition
occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer’s position is outside the 2-
Bit window. The JA has a typical clock delay equal to ½ of the FIFO bit depth.
N
In single rail mode, RPOS is the output of decoded AMI or HDB3 signals and RNEG is the LCV output. HDB3
data is defined as any block of 4 successive zeros replaced with OOOV or BOOV, so that two successive V
pulses are of opposite polarity to acheive zero DC offset. If the HDB3 decoder is selected, the receive path
removes the V and B pulses so that the original data is output to RPOS.
1.5
1.6
1.4.1
1.4.2
1.4.3
OTE
: If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the JA can be
configured in the transmit path to smooth out the gapped clock. See the Transmit Section of this datasheet.
Receive Jitter Attenuator
HDB3 Decoder
RLOS (Receiver Loss of Signal)
AIS (Alarm Indication Signal)
LCV (Line Code Violation Detection)
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
17
XRT83SL216