XRT83SL216ES Exar, XRT83SL216ES Datasheet - Page 32

• Manufacturer Part Number: XRT83SL216ES
• Description: Peripheral Drivers & Components - PCIs 16 CH E1 LIU SH
• Manufacturer: Exar

Specifications of XRT83SL216ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83SL216
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
N
Channel 14 Control Register (0x2Eh - 0x30h)
Channel 15 Control Register (0x31h - 0x33h)
R
OTE
48
49
50
51
52
53
EG
B
: * Indicates that these bits are WRITE-ONLY Reset for that channel register only.
D7
D6
D5
D4
D3
IT
ADDR T
0x30
0x31
0x32
0x33
0x34
0x35
Reserved
RUR/
RUR/
R/W
R/W
R/W
R/W
SR/DR
RO
RO
FIFOS
YPE
CODE
N
GIE
AME
SRES_14 *
SRES_15 *
Reserved
Reserved
Reserved
Reserved
D7
T
Global Interrupt Enable
The global interrupt enable is used to enable/disable all interrupt
activity for all 16 channels. This bit must be set "High" for the inter-
rupt pin to operate.
"0" = Disable all interrupt generation
"1" = Enable interrupt generation to the individual channel registers
This Register Bit is Not Used
Single Rail / Dual Rail Select
This bit is used to configure the receive outputs and transmit inputs
to single rail or dual rail data formats.
"0" = Dual Rail
"1" = Single Rail
Encoding / Decoding Select (Single Rail Mode Only)
This bit is used to select between AMI or HDB3.
"0" = HDB3
"1" = AMI
FIFO Depth Select
The FIFO depth select is used to configure the part for a 32-bit or
64-bit FIFO (Within the Jitter Attenuator Block). The delay of the
FIFO is typically equal to ½ the FIFO depth.
"0" = 32-bit FIFO
"1" = 64-bit FIFO
ABLE
G
T
LOBAL
ABLE
7: M
ARAOS_14
ARAOS_15
AISIE_14
AISIS_14
AISIE_15
AISIS_15
D6
ICROPROCESSOR
C
6: M
ONTROL
ICROPROCESSOR
ATAOS_14
DMOIE_14
DMOIS_14
ATAOS_15
DMOIE_15
DMOIS_15
R
D5
EGISTER FOR
F
UNCTION
R
EGISTER
30
RLOSIE_14
RLOSIS_14
RLOSIE_15
RLOSIS_15
TAOS_14
TAOS_15
R
D4
A
EGISTER
LL
16 C
0
X
00
HANNELS
RLAM_14
RLAM_15
Reserved
Reserved
Reserved
Reserved
H
D
D3
B
ESCRIPTION
IT
D
ESCRIPTION
(0
X
00
TXOE_14
TXOE_15
Reserved
Reserved
AISS_14
AISS_15
H
D2
)
Register
RCLKinv_14
RCLKinv_15
DMOS_14
DMOS_15
Type
R/W
R/W
R/W
R/W
R/W
LPB1
LPB1
D1
(HW reset)
TCLKinv_14
TCLKinv_15
RLOSS_14
RLOSS_15
REV. 1.0.0
Default
Value
LPB0
LPB0
D0
0
0
0
0
0