89H48H12G3YCHLG IDT, 89H48H12G3YCHLG Datasheet - Page 10

• Manufacturer Part Number: 89H48H12G3YCHLG
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H48H12G3YCHLG

• Rohs: yes

IDT 89HPES48H12G2 Data Sheet
REFRES[13,12,9:0]
JTAG_TRST_N
REFRESPLL
JTAG_TCK
JTAG_TDO
JTAG_TMS
JTAG_TDI
V
V
V
Signal
Signal
V
DD
DD
V
DD
DD
DD
V
CORE
PEHA
PETA
SS
PEA
I/O
Type
Type
O
I/O
I/O
I
I
I
I
Table 7 Power, Ground, and SerDes Resistor Pins
I
I
I
I
I
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
External Reference Resistors. Provides a reference for the SerDes bias
currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be
connected from these pins to ground.
PLL External Reference Resistor. Provides a reference for the PLL bias
currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be
connected from this pin to ground.
Core V
I/O V
PCI Express Analog Power. Serdes analog power supply (1.0V).
PCI Express Analog High Power. Serdes analog power supply (2.5V).
PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
Ground.
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
DD.
DD.
LVTTL I/O buffer power supply (2.5V or preferred 3.3V).
Table 6 Test Pins
Power supply for core logic (1.0V).
10 of 44
Name/Description
Name/Description
November 28, 2011