89H48H12G3YCHLG IDT, 89H48H12G3YCHLG Datasheet - Page 2

• Manufacturer Part Number: 89H48H12G3YCHLG
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H48H12G3YCHLG

• Rohs: yes

IDT 89HPES48H12G2 Data Sheet
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– All ports support hot-plug using low-cost external I
– Configurable presence detect supports card and cable appli-
– GPE output pin for hot-plug event notification
– Hot swap capable I/O
– Supports D0, D3hot and D3 power management states
– Active State Power Management (ASPM)
– Supports PCI Express Power Budgeting Capability
– SerDes power savings
– ECRC support
– AER on all ports
– SECDED ECC protection on all internal RAMs
– End-to-end data path parity protection
– Checksum Serial EEPROM content protected
– Autonomous link reliability (preserves system operation in the
– Ability to generate an interrupt (INTx or MSI) on link up/down
– On-chip link activity and status outputs available for Port 0
– Per port link activity and status outputs available using
– SerDes test modes
– Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
– Requires only two power supply voltages (1.0 V and 2.5 V)
– No power sequencing requirements
Power Management
9 General Purpose I/O
Reliability, Availability and Serviceability (RAS)
Test and Debug
Power Supplies
Packaged in a 27mm x 27mm 676-ball Flip Chip BGA with
1mm ball spacing
• Enables SCI/SMI generation for legacy operating system
• Supports L0, L0s, L1, L2/L3 Ready and L3 link states
• Configurable L0s and L1 entry timers allow performance/
• Supports low swing / half-swing SerDes operation
• SerDes optionally turned-off in D3hot
• SerDes associated with unused ports are turned-off
• SerDes associated with unused lanes are placed in a low
expanders
cations
presence of faulty links)
transitions
(upstream port)
external I
Note that a 3.3V is preferred for V
support
power-savings tuning
power state
2
C I/O expander for all other ports
DD
I/O
2
C I/O
2 of 44
Product Description
PES48H12G2 provides the most efficient system interconnect switching
solution for applications requiring high throughput, low latency, and
simple board layout with a minimum number of board layers. It provides
48 GBps (384 Gbps) of aggregated, full-duplex switching capacity
through 48 integrated serial lanes, using proven and robust IDT tech-
nology. Each lane is capable of 5 GT/s of bandwidth in both directions
and is fully compliant with PCI Express Base specification 2.0.
tecture. The PCI Express layer consists of SerDes, Physical, Data Link
and Transaction layers in compliance with PCI Express Base specifica-
tion Revision 2.0. The PES48H12G2 can operate either as a store and
forward or cut-through switch. It supports eight Traffic Classes (TCs)
and one Virtual Channel (VC) with sophisticated resource management
to enable efficient switching and I/O connectivity for servers, storage,
and embedded processors with limited connectivity.
addition to operating as a standard PCI express switch, the
PES48H12G2 ports may be partitioned into groups that logically
operate as completely independent PCIe switches. Figure 2 illustrates a
three partition PES48H12G2 configuration.
Utilizing
The PES48H12G2 is based on a flexible and efficient layered archi-
The PES48H12G2 is a partitionable PCIe switch. This means that in
standard
PCI
Express
Gen2
November 28, 2011
interconnect,
the