89H48H12G3YCHLG IDT, 89H48H12G3YCHLG Datasheet - Page 9

• Manufacturer Part Number: 89H48H12G3YCHLG
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H48H12G3YCHLG

• Rohs: yes

IDT 89HPES48H12G2 Data Sheet
SWMODE[3:0]
RSTHALT
Signal
PERSTN
Type
I
I
I
Global Reset. Assertion of this signal resets all logic inside PES48H12G2.
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES48H12G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the PES48H12G2
switch operating mode. Note: These pins should be static and not change
following the negation of PERSTN.
0x0 - Single partition
0x1 - Single partition with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Single partition with port 0 selected as the upstream port (port 2 dis-
0x9 - Single partition with port 2 selected as the upstream port (port 0 dis-
0xA - Single partition with Serial EEPROM initialization and port 0 selected
0xB - Single partition with Serial EEPROM initialization and port 2 selected
0xC - Multi-partition
0xD - Multi-partition with Serial EEPROM initialization
0xE - Reserved
0xF - Reserved
Table 5 System Pins (Part 2 of 2)
abled)
abled)
as the upstream port (port 2 disabled)
as the upstream port (port 0 disabled)
9 of 44
Name/Description
November 28, 2011