PCF8576DT/S400/2,1 NXP Semiconductors, PCF8576DT/S400/2,1 Datasheet - Page 22

• Manufacturer Part Number: PCF8576DT/S400/2,1
• Description: LCD Drivers 2.64KHz 50mA 400mW
• Manufacturer: NXP Semiconductors

Specifications of PCF8576DT/S400/2,1

• Rohs: yes
• Maximum Clock Frequency: 2.64 kHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Package / Case: TSSOP-56
• Maximum Power Dissipation: 400 mW
• Maximum Supply Current: 50 mA
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2000

NXP Semiconductors
PCF8576D
Product data sheet
7.10.4 Writing over the RAM address boundary
7.10.5 Output bank selector
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in
Table 7.
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
In the case described in
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows:
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be considered in the module
layout process as well as in the driver software design.
In all multiplex drive modes, depending on the setting of the data pointer, it is possible to
fill the RAM over the RAM address boundary. If the PCF8576D is part of a cascade the
additional bits fall into the next device that also generates the acknowledge signal. If the
PCF8576D is a single device or the last device in a cascade the additional bits will be
discarded and no acknowledge signal will be generated.
The output bank selector (see
address for transfer to the display register. The actual row selected depends on the
selected LCD drive mode in operation and on the instant in the multiplex sequence.
The PCF8576D includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank-select command may request the contents
of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex
Display RAM
bits (rows)/
backplane
outputs (BPn)
0
1
2
3
•
•
•
•
•
•
•
In the first write to the RAM, bits a7 to a0 are written.
In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, 2, and then 3
In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
In 1:2 multiplex mode, rows 0 and 1 are selected
In static mode, row 0 is selected
Entire RAM filling by rewriting in 1:3 multiplex drive mode
All information provided in this document is subject to legal disclaimers.
Display RAM addresses (columns)/segment outputs (Sn)
0
a7
a6
a5
-
Rev. 13 — 10 May 2012
1
a4
a3
a2
-
Table 7
Table
2
a1/b7 b4
a0/b6 b3
b5
-
the RAM has to be written entirely and BP2/S2, BP2/S5,
14) selects one of the four rows per display RAM
3
b2
-
Universal LCD driver for low multiplex rates
4
b1/c7 c4
b0/c6 c3
c5
-
5
c2
-
6
c1/d7 d4
c0/d6 d3
d5
-
Table
7
d2
-
7.
PCF8576D
8
d1/e7 e4
d0/e6 e3
e5
-
© NXP B.V. 2012. All rights reserved.
9
e2
-
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