PCF8576DT/S400/2,1 NXP Semiconductors, PCF8576DT/S400/2,1 Datasheet - Page 8

• Manufacturer Part Number: PCF8576DT/S400/2,1
• Description: LCD Drivers 2.64KHz 50mA 400mW
• Manufacturer: NXP Semiconductors

Specifications of PCF8576DT/S400/2,1

• Rohs: yes
• Maximum Clock Frequency: 2.64 kHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Package / Case: TSSOP-56
• Maximum Power Dissipation: 400 mW
• Maximum Supply Current: 50 mA
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2000

NXP Semiconductors
PCF8576D
Product data sheet
7.1 Power-On Reset (POR)
7.2 LCD bias generator
The host microcontroller maintains the 2-line I
PCF8576D. The internal oscillator is enabled by connecting pin OSC to pin V
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are to the power supplies
(V
At power-on the PCF8576D resets to the following starting conditions:
Remark: Do not transfer data on the I
the reset action to complete.
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between pins V
by switch if the
selected. The LCD voltage can be temperature compensated externally using the supply
to pin V
Fig 5.
•
•
•
•
•
•
•
DD
All backplane and segment outputs are set to V
The selected drive mode is: 1:4 multiplex with
Blinking is switched off
Input and output bank selectors are reset
The I
The data pointer and the subaddress counter are cleared (set to logic 0)
The display is disabled (bit E = 0, see
, V
V
V
SS
LCD
SS
DD
CONTROLLER
PROCESSOR/
2
The resistance of the power lines must be kept to a minimum.
For chip-on-glass applications, due to the Indium Tin Oxide (ITO) track resistance, each supply line
must be routed separately between the chip and the connector.
Typical system configuration
, and V
C-bus interface is initialized
MICRO-
MICRO-
.
HOST
R ≤
1
All information provided in this document is subject to legal disclaimers.
⁄
2
LCD
2C
bias voltage level for the 1:2 multiplex drive mode configuration is
t
r
B
) and the LCD panel chosen for the application.
Rev. 13 — 10 May 2012
OSC
SDA
SCL
2
C-bus for at least 1 ms after a power-on to allow
A0
LCD
Table
Universal LCD driver for low multiplex rates
PCF8576D
A1
V
and V
DD
2
A2
C-bus communication channel with the
11)
V
SS
LCD
1
SA0
⁄
LCD
3
. The center impedance is bypassed
bias
V
SS
40 segment drives
4 backplanes
PCF8576D
© NXP B.V. 2012. All rights reserved.
LCD PANEL
(up to 160
elements)
SS
mdb079
. The
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