ISL1902FAZ-T7A Intersil, ISL1902FAZ-T7A Datasheet - Page 15

• Manufacturer Part Number: ISL1902FAZ-T7A
• Description: LED Lighting Drivers Dimmable AC Mains LED Driver PFC
• Manufacturer: Intersil

Specifications of ISL1902FAZ-T7A

• Rohs: yes
• Input Voltage: 4 V
• Operating Frequency: 320 Hz
• Maximum Supply Current: 14.5 mA
• Output Current: 1 A
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-24
• Minimum Operating Temperature: - 40 C

The first calculation required is to determine the required
secondary inductance.
The turns ratio N
N
Knowing the secondary inductance and the turns ratio, the
primary inductance can be calculated.
L
With this information, the lowest switching frequency, which
occurs at maximum load and at the peak instantaneous input
voltage at the minimum RMS voltage, can be determined. By
setting the maximum duty cycle and picking a typical average
frequency, the ON-time is already known.
t
The primary peak current at the end of the ON-time is:
I
The peak secondary current is the peak primary current divided
by the transformer turns ratio.
I
And the OFF-time is:
t
The lowest switching frequency is the reciprocal of the sum of the
ON-time, the OFF-time, and the delay time.
f
The delay time can be approximated if the equivalent
drain-source capacitance (C
This value should also include any parasitic capacitance on the
drain node. These parameters may not be known during the early
stages of the design, but the required delay is typically on the
order of 300ns to 500ns.
t
If the lowest frequency does not meet the design requirements,
iterative calculations may be required.
The highest frequency is determined by the shortest ON-time
summed with t
minimum load, and occurs at or near the AC zero crossing when
the primary (and secondary) current is zero. The minimum
non-zero ON-time is ~100ns, suggesting an operating frequency
L
ON
p peak
s peak
OFF
min
delay
p
s
sp
(
(
=
=
=
=
=
------------ -
N
=
V
------------------------------------------- -
≈
f
--------------------------------------------------- -
η V
L
---------------------- -
f
)
)
typ avg
sp
--------------------------------------------------- -
t
o
typ avg
ON
π
-----------------------------------------------------------------
L
------------------------------- -
s
D
=
⋅
=
⋅
V
s
2
⋅
max
(
(
(
o
⋅
1 D
V
--------------------------------------- -
I
--------------------- -
mINrms
+
p peak
I
⋅
L
s peak
V
–
rms
(
(
N
t
p
(
OFF
o
1 D
)
)
sp
⋅
delay
⋅
max
–
H
1
(
2 I
⋅
sp
C
L
)
⋅
+
p
oss
)
max
2
⋅
2 t
is calculated next.
)
. The shortest ON-time occurs at high line and
o
t
D
2
s
delay
⋅
max
+
ON
)
C
s
s
other
H
OSS
15
)
A
Hz
) of the primary switch is known.
s
(EQ. 10)
(EQ. 2)
(EQ. 3)
(EQ. 4)
(EQ. 5)
(EQ. 6)
(EQ. 7)
(EQ. 8)
(EQ. 9)
ISL1902
above 1MHz. In any event, the maximum frequency clamp would
become active at around 800kHz. Once the primary and
secondary inductances are known, the general formulae to
calculate the ON-time and OFF-time at an equivalent DC input
voltage are:
t
t
It is clear from these equations that there is a linear relationship
between load current and frequency. At some light load, the
frequency will be limited by the maximum frequency clamp. The
frequency has an inverse relationship to input voltage and has a
less significant affect over a typical operating range.
It should be noted, however, that the above equations assume
full conduction angle of the AC mains. When conduction angle
modulating dimmers are used to block a portion of each AC
half-cycle, the switching currents remain essentially unchanged
during the conduction portion of the AC half-cycle as the
conduction angle is reduced. The result being that the steady
state frequency behavior will not vary much as the conduction
angle is reduced from full. If an analog control signal is used
instead, the frequency behavior will be as predicted above.
THE SEPIC TOPOLOGY
The SEPIC topology, in simplified form, is shown in Figure 12. The
voltage source indicated may be either DC or rectified AC. The
capacitance of C
PFC.
The terminology defined in Table 1 shall be reused, except Ls and
Lp are replaced by L1 and L2 per Figure 12. In steady state
operation, the average voltage across L1 and L2 must be zero. If
this were not true, saturation would occur. Furthermore, this
situation implies the voltage across C1 must be equal to the
input source voltage, V
conducting, the voltage across each inductor is V
OFF-time, Q1 is off, and the voltage across each inductor is -V
Since no DC current may flow through C1, the output current, I
must be equal to the average current flowing in L2. Additionally,
I
the OFF-time.
To determine the values of L1 and L2, the operating conditions
must be defined. The lowest operating frequency occurs at
maximum load and minimum input voltage. If operating from
and AC source, the lowest frequency occurs at the instantaneous
OFF
ON
O
is also the average current that flows in both inductors during
+
_
=
=
2 L
------------------------------------- -
2 L
---------------------- -
⋅
⋅
V
V
p
INrms
s
o
⋅
⋅
N
I
C
o
sp
IN
⋅
IN
⋅
⎛
⎜
⎝
1
I
FIGURE 12. SEPIC TOPOLOGY
is negligibly small for applications requiring
o
L1
+
⋅
L
-------------------------------- -
⎛
⎜
⎝
L
IN
1
p
s
+
. During the ON-time, when switch Q1 is
⋅
⋅
N
V
L
-------------------------------- -
L
sp
p
INrms
s
⋅
⋅
⋅
N
V
V
sp
INrms
Q1
o
⎞
⎟
⎠
⋅
C1
V
o
⎞
⎟
⎠
s
L2
s
D1
IN
C
. During the
OUT
March 20, 2013
FN7981.2
(EQ. 11)
(EQ. 12)
OUT
L
O
A
D
O
,
.