ISL1902FAZ-T7A Intersil, ISL1902FAZ-T7A Datasheet - Page 16

• Manufacturer Part Number: ISL1902FAZ-T7A
• Description: LED Lighting Drivers Dimmable AC Mains LED Driver PFC
• Manufacturer: Intersil

Specifications of ISL1902FAZ-T7A

• Rohs: yes
• Input Voltage: 4 V
• Operating Frequency: 320 Hz
• Maximum Supply Current: 14.5 mA
• Output Current: 1 A
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-24
• Minimum Operating Temperature: - 40 C

peak of the AC voltage waveform at the lowest RMS input
voltage. Therefore, the lowest DC or equivalent DC (RMS) input
voltage is used as the design point with a corresponding
selection of a minimum desired operating frequency.
During the ON-time, the current in L2 ramps from zero to a peak
value, I
I
where V
voltage. During the OFF-time, the current ramps from I
down to zero at a rate determined by V
I
Since the average value of current in L2 must be the load current,
I
input voltage values for t
t
t
Equations 15 and 16 may be summed to provide an equivalent
switching period for the equivalent DC (RMS) input and stated
design parameters, and the value for L2 may be calculated. For
DC input applications, the calculation is straight forward.
t
where t
“Quasi-Resonant Switching”.
L2
When the input voltage is rectified AC, the desired switching
period has to be modified to account for the difference between
the RMS voltage and the instantaneous peak of the AC
waveform. The frequency is lower at the AC peak than at the
equivalent DC (RMS) input voltage.
t
Using Equation 19 for t
the appropriate value for L2 in rectified AC input applications.
As stated previously, both inductor currents flow to the output
during the OFF-time. I
of both inductor currents during the OFF-time over a complete
switching cycle.
I
Using Equations 15 and 16 and solving for L1 yields:
L1
P
P
O
ON
OFF
S
S
O
, Equations 13 and 14 can be used to relate the DC or RMS
=
=
=
=
=
=
=
=
V
-------------------------------------------------- -
V
---------------------------------
t
----------------------------------------- -
2
=
ON
----------------------------------------------------------------------------------------- -
2 I
V
----------------------------------------------- -
2
IN minRMS
OUT
----------------------------------- -
V
V
⋅
P
IN minRMS
delay
⋅
IN(minRMS)
I
------------------------ -
.
(
IN minRMS
⋅
OUT
O
(
I
t
+
OUT
(
(
O
V
ON
L2
t
t
(
⋅
S
ON
t
OUT
⋅
⋅
V
2 L2
OFF
⋅
t
2 L2
L2
is a constant and defined in the next section,
OUT
OFF
⋅
+
⋅
V
⋅
t
⋅
+
OUT
2
OFF
t
(
OFF
V
t
+
OFF
)
OUT
t
)
delay
⋅
)
⋅
t
⋅
)
is defined as the minimum DC or RMS input
L2
ON
V
)
⋅
O
⎛
⎝
IN minRMS
+
+
s
A
------ -
L1
S
1
V
t
may be solved for by averaging the sum
(
delay
ON
and substituting into Equation 18 yields
s
IN minRMS
+
(
------ -
L2
H
and t
A
1
s
16
⎞
⎠
)
OFF
s
)
A
)
to I
OUT
O
.
.
H
P
back
(EQ. 13)
(EQ. 14)
(EQ. 15)
(EQ. 18)
(EQ. 19)
(EQ. 20)
(EQ. 16)
(EQ. 17)
(EQ. 21)
ISL1902
The final step in specifying the inductor requirements is to
determine the DC bias on each inductor. Earlier it was assumed
that each inductor current ramps from zero to some peak value
during the ON-time. In reality each inductor has a DC bias current
that does not contribute to the output current and may be
ignored in the previous calculations, but its value is required to
determine the RMS currents in each inductor. The reason the DC
bias exists is that there can be no DC current through C1 (see
Figure 12). The current flowing from L2 into C1 during the ON-
time must equal the current flowing in the opposite direction
from L1 during the OFF-time.
I
where I
cycle, I
can also be used on a cycle-by-cycle basis providing
instantaneous values of T
Equation 22 equal to zero and solving for I
I
which represents the DC bias current flowing from L1 through C1
into L2 at the equivalent DC (RMS) input voltage. It may be
thought of as the expected value of bias current. In rectified AC
input applications, the bias current varies as needed each
switching cycle to balance charge on C1 as the AC voltage varies
from valley to peak to valley during each AC half-cycle.
Quasi-Resonant Switching
The ISL1902 uses critical conduction mode PWM control
algorithm. Near zero voltage switching (ZVS) or quasi-resonant
switching, as it is sometimes referred to, can be achieved in the
flyback topology by delaying the next switching cycle after the
transformer current decays to zero (critical conduction mode).
The delay allows the primary inductance and capacitance to
oscillate, causing the switching FET drain-source voltage to ring
down to a minima. If the FET is turned on at this minima, the
capacitive switching loss (1/2 CV
C1
DC
=
=
I
DC
I
DC
C1
O
⋅
is the DC bias current, and T
+
is the current through C1 during a complete switching
---------------------------------------------------------- -
V
V
0
0
IN minRMS
IN minRMS
V
---------------------------------
OUT
2 L1 t
-V
(
(
⋅
T
O U T
O N
FIGURE 13. SEPIC WAVEFORMS
⋅
t
⋅
2
OFF
S
)
)
–
+
–
V
V
ON
V
----------------------------------------------------- -
I
I
T s
OUT
OUT
V
L 1
V
L 2
IN minRMS
, T
IN
L 1 ,
T
(
O F F
OFF
2 L2 t
V
⋅
L 2
2
) is greatly reduced.
and V
A
⋅
S
)
S
= T
⋅
t
IN
2
OFF
ON
DC
are used. Setting
+ T
yields Equation 23,
t
d e la y
OFF
A
. Equation 22
March 20, 2013
t
t
FN7981.2
(EQ. 22)
(EQ. 23)