MCIMX6S4AVM08ABR Freescale Semiconductor, MCIMX6S4AVM08ABR Datasheet - Page 125

• Manufacturer Part Number: MCIMX6S4AVM08ABR
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S4AVM08ABR

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: Parallel
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Table 82
delay, setup, and hold times.
Freescale Semiconductor
1
2
Cycle-to-cycle system jitter
Transmitter MLBSP/N (MLBDP/N) output
valid from transition of MLBCP/N
(low-to-high)
Disable turnaround time from transition of
MLBCP/N (low-to-high)
Enable turnaround time from transition of
MLBCP/N (low-to-high)
MLBSP/N (MLBDP/N) valid to transition of
MLBCP/N (low-to-high)
MLBSP/N (MLBDP/N) hold from transition
of MLBCP/N (low-to-high)
t
ered-to-external clock ratios.
The transmitting device must ensure valid data on MLBSP/N (MLBDP/N) for at least t
BCP/N; receivers must latch MLBSP/N (MLBDP/N) data within t
delay
1
2
3
MLBSIG/MLBDAT output high
impedance from MLBCLK low
Bus Hold from MLBCLK low
MLBSIG/MLBDAT output valid
from transition of MLBCLK (low
to high)
, t
The controller can shut off MLBCLK to place MediaLB in a low-power state. Depending on the time the clock is
shut off, a runt pulse can occur on MLBCLK.
MLBCLK low/high time includes the pulse width variation.
The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state
of the final driven bit on the line must remain on the bus for t
meeting the maximum load capacitance listed.
phz
lists the MediaLB 6-pin interface timing characteristics, and
, t
1
plz
, t
Parameter
Parameter
su
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
, and t
hd
2
may also be referenced from a low-to-high transition of the recovered clock for 2:1 and 4:1 recov-
Table 81. MLB 1024 Fs Timing Parameters (continued)
Table 82. MLB 6-Pin Interface Timing Parameters
Symbol
t
t
t
mcfdz
mdzh
delay
Symbol
t
t
delay
t
t
jitter
t
t
phz
plz
su
hd
Min
—
0
2
0.05
Min
0.6
0.6
0.6
0.6
—
hd(min)
Max
t
mdzh
mckl
—
7
of the rising edge of MLBCP/N.
. Therefore, coupling must be minimized while
Max
600
1.3
3.5
5.6
—
Unit
ns
ns
ns
Figure 87
Unit
ps
ns
ns
ns
ns
hd(min)
following the rising edge of ML-
—
shows the MLB 6-pin
Electrical Characteristics
Comment
—
—
3
Comment
125