MCIMX503CVK8B Freescale Semiconductor, MCIMX503CVK8B Datasheet - Page 52

no-image

MCIMX503CVK8B

Manufacturer Part Number
MCIMX503CVK8B
Description
Processors - Application Specialized CODEX 13MM REV 1.1
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet

Specifications of MCIMX503CVK8B

Core
ARM Cortex A8
Processor Series
i.MX50
Data Bus Width
32 bit
Operating Supply Voltage
0.75 V to 1.275 V
Memory Type
L1/L2 Cache, ROM, SRAM

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX503CVK8BR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Electrical Characteristics
1
2
3
52
GPMI’s Async Mode output timing could be controlled by module’s internal register, say
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers’ setting. In the above table, we use AS/DS/DH representing these settings each.
T represents for the GPMI clock period.
AS minimum value could be 0, while DS/DH minimum value is 1.
NF10
NF11
NF12
NF13
NF14
NF15
NF16
NF17
NF5
NF6
NF7
NF8
NF9
ID
WE pulse width
Write cycle time
WE hold time
Ready to RE low
RE pulse width
READ cycle time
RE high hold time
Data setup on read
Data hold on read
ALE setup time
ALE hold time
Data setup time
Data hold time
Parameter
Table 39. Asynchronous Mode Timing Parameters
i.MX50 Applications Processors for Consumer Products, Rev. 4
Symbol
tREH
tDSR
tDHR
tALH
tALS
tWC
tWH
tWP
tDH
tRR
tRP
tRC
tDS
(DS+DH)*T
(DH+1)*T
T
(AS+1)*T
(AS+1)*T
2
DS*T
DH*T
DS*T
Min.
= GPMI Clock Cycle
(DS+DH)*T
Timing
DS*T
DH*T
DH*T
N/A
N/A
Max.
3
1
(continued)
GPMI Clock
Example Timing for
Min.
10
20
10
10
10
10
20
10
10
10
T = 10ns
10
20
10
Freescale Semiconductor
≈ 100
Max.
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Related parts for MCIMX503CVK8B