MCIMX503CVK8B Freescale Semiconductor, MCIMX503CVK8B Datasheet - Page 70
MCIMX503CVK8B
Manufacturer Part Number
MCIMX503CVK8B
Description
Processors - Application Specialized CODEX 13MM REV 1.1
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX503EVM8B.pdf
(135 pages)
Specifications of MCIMX503CVK8B
Core
ARM Cortex A8
Processor Series
i.MX50
Data Bus Width
32 bit
Operating Supply Voltage
0.75 V to 1.275 V
Memory Type
L1/L2 Cache, ROM, SRAM
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Electrical Characteristics
4.8.3
The DRAM data output timing is defined for all DDR types: DDR2, LPDDR1, and LPDDR2.
70
CK >= 200 MHz
DDR10
DDR11
DDR12
DDR13
DDR14
DDR15
ID
DRAM Data Output Timing
DRAM_SDCLK_B
DRAM_SDCLK
DRAM_SDQS_B
DRAM_SDQS
DRAM_D &
DRAM_DQM
DDR6 and DDR7 can be adjusted by the parameter -DLL_WR_DELAY-;
The ideal case is that SDCLK is center aligned to the DRAM_A[9:0] data
valid window;
For this table, HW_DRAM_PHY23[14:8] (DLL_WR_DELAY) = 0x10;
Positive DQS latching edge to associated CK edge
DQS falling edge from CK rising edge—hold time
DQS falling edge to CK rising edge—setup time
DQS output high pulse width
DQS output low pulse width
DQ & DQM output setup time relative to DQS
i.MX50 Applications Processors for Consumer Products, Rev. 4
Figure 30. DRAM Data Output Timing
Description
Table 46. DDR Output AC Timing
DDR10
DDR13
NOTE
d0
d1
DDR11
DDR15
Symbol
DDR16
tDQSS
tDQSH
tDQSL
d2
tDSH
tDSS
tDS
DDR14
d3
0.48 tCK
0.48 tCK
0.5 tCK
0.5 tCK
0.5 tCK
DDR12
- 0.3
- 0.3
- 1.3
Min
-0.3
Freescale Semiconductor
0.52 tCK
0.52 tCK
0.5 tCK
0.5 tCK
+ 0.3
+ 0.3
Max
0.3
—
Unit
ns
ns
ns
ns
ns
ns
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