IS62C1024AL-35TLI ISSI, Integrated Silicon Solution Inc, IS62C1024AL-35TLI Datasheet - Page 7

• Manufacturer Part Number: IS62C1024AL-35TLI
• Description: IC SRAM 1MBIT 35NS 32TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: Asynchronousr

Specifications of IS62C1024AL-35TLI

• Memory Size: 1M (128K x 8)
• Package / Case: 32-TSOP
• Interface: Parallel
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 35ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 35 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 30 mA
• Organization: 128 K x 8
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 706-1042

AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)
IS62C1024AL
IS65C1024AL
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. H
06/26/08
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
2. I/O will assume the High-Z state if OE = V
ADDRESS
ADDRESS
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
DOUT
DOUT
CE1
CE2
DIN
WE
CE1
CE2
DIN
WE
t
DATA UNDEFINED
DATA UNDEFINED
SA
t
SA
Ih
.
t
HZWE
t
(1,2)
AW
t
HZWE
t
AW
t
PWE
t
t
SCE1
SCE2
t
SCE1
(1,2)
t
t
1-800-379-4774
t
SCE2
PWE
WC
(4)
t
WC
(4)
HIGH-Z
HIGH-Z
t
SD
t
DATA-IN VALID
SD
DATA-IN VALID
t
HA
t
t
t
LZWE
HD
HA
t
t
HD
LZWE
7