IS61WV25616BLL-10TLI ISSI, Integrated Silicon Solution Inc, IS61WV25616BLL-10TLI Datasheet - Page 13

• Manufacturer Part Number: IS61WV25616BLL-10TLI
• Description: IC SRAM 4MBIT 10NS 44TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61WV25616BLL-10TLI

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 4M (256K x 16)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSOP II
• Density: 4Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 18b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 40mA
• Operating Supply Voltage (min): 2.4V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1106; IS61WV25616BLL-10TLI

IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
07/15/2010
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
WC
HD
SCE
AW
HA
SA
PWB
PWE
PWE
SD
HZWE
LZWE
V
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write.
DD
1
2
(3)
(3)
-0.3V and output loading specified in Figure 1a.
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
Min.
20
12
12
12
12
17
—
0
0
9
0
3
-20 ns
Max.
—
—
—
—
—
—
—
—
—
—
—
9
Min.
25
18
15
18
18
20
12
—
(1,2)
0
0
0
5
-25 ns
(Over Operating Range)
Max.
12
—
—
—
—
—
—
—
—
—
—
—
Min.
35
25
25
30
30
30
15
—
0
0
0
5
-35 ns
Max.
—
—
—
—
—
—
—
—
—
—
20
—
Min.
45
35
35
35
35
35
20
—
0
0
0
5
-45ns
Max.
—
—
—
—
—
—
—
—
—
—
20
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
1
2
3
4
5
6
7
8
9
10
11
12