S9S08DZ60F2MLF Freescale Semiconductor, S9S08DZ60F2MLF Datasheet - Page 111

• Manufacturer Part Number: S9S08DZ60F2MLF
• Description: 8-bit Microcontrollers - MCU M74K MASK ONLY-AUTO
• Manufacturer: Freescale Semiconductor

Specifications of S9S08DZ60F2MLF

• Rohs: yes
• Core: HCS08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 60 KB
• Data Ram Size: 4 K
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Processor Series: MC9S08DZ60

6.5.7
Port G is controlled by the registers listed below.
6.5.7.1
6.5.7.2
Freescale Semiconductor
PTGDD[5:0]
PTGD[5:0]
Reset:
Reset:
Field
Field
5:0
5:0
W
W
R
R
Port G Registers
Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups disabled.
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
Port G Data Register (PTGD)
0
0
Port G Data Direction Register (PTGDD)
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 6-43. Port G Data Direction Register (PTGDD)
Table 6-41. PTGDD Register Field Descriptions
Table 6-40. PTGD Register Field Descriptions
Figure 6-42. Port G Data Register (PTGD)
PTGDD5
MC9S08DZ60 Series Data Sheet, Rev. 4
PTGD5
0
0
5
5
PTGDD4
PTGD4
0
0
4
4
Description
Description
PTGDD3
PTGD3
3
0
3
0
PTGDD2
PTGD2
Chapter 6 Parallel Input/Output Control
0
0
2
2
PTGDD1
PTGD1
0
0
1
1
PTGDD0
PTGD0
0
0
0
0
111