CY7C1515AV18-200BZC Cypress Semiconductor Corp, CY7C1515AV18-200BZC Datasheet - Page 25

• Manufacturer Part Number: CY7C1515AV18-200BZC
• Description: IC SRAM 72MBIT 200MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1515AV18-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-06985 Rev. *D
Parameter
Output Times
t
t
t
t
t
t
t
t
t
t
DLL Timing
t
t
t
26. These parameters are extrapolated from the input timing parameters (t
27. t
28. At any voltage and temperature t
CO
DOH
CCQO
CQOH
CQD
CQDOH
CQH
CQHCQH
CHZ
CLZ
KC Var
KC lock
KC Reset
Cypress
included in the t
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in (b) of
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
CHQZ
CHQX1
KC Var
KC lock
KC Reset
Parameter
KHKH
). These parameters are only guaranteed by design and are not tested in production
C/C Clock Rise (or K/K in single
clock mode) to Data Valid
Data Output Hold after Output C/C
Clock Rise (Active to Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock
Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge)
Clock (C/C) Rise to High-Z
(Active to High-Z)
Clock (C/C) Rise to Low-Z
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
[22, 23]
CHZ
is less than t
Description
(continued)
CLZ
[27, 28]
and t
CHZ
[27, 28]
less than t
[26]
[26]
AC Test Loads and
KHKH
CO
–0.27
–0.45
–0.45
–0.45
1024
1.24
1.24
Min Max Min Max Min Max Min Max Min Max
- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
.
300 MHz
30
–
–
–
–
0.45
0.45
0.27
0.45
0.20
–
–
–
–
–
–
–
Waveforms. Transition is measured ± 100 mV from steady-state voltage.
–0.45
–0.45
–0.27
–0.45
1024
1.35
1.35
278 MHz
30
–
–
–
–
CY7C1513AV18, CY7C1515AV18
CY7C1511AV18, CY7C1526AV18
0.45
0.45
0.27
0.45
0.20
–
–
–
–
–
–
–
–0.45
–0.45
–0.30
–0.45
1024
1.55
1.55
250 MHz
30
–
–
–
–
0.45
0.45
0.30
0.45
0.20
–
–
–
–
–
–
–
–0.45
–0.45
–0.35
–0.45
1024
1.95
1.95
200 MHz
30
–
–
–
–
0.45
0.45
0.35
0.45
0.20
–
–
–
–
–
–
–
–0.50
–0.50
–0.40
–0.50
1024
2.45
2.45
167 MHz
30
–
–
–
–
KC Var
Page 25 of 31
0.50
0.50
0.40
0.50
0.20
) is already
–
–
–
–
–
–
–
Cycles
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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