MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 21

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

Commands
Table 8:
Table 9:
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Truth Table – Commands
Notes 1 and 10 apply to all commands
Truth Table – DM Operation
Note 1 applies to all commands
Name (Function)
Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH.
Notes: 1. Used to mask write data; provided coincident with the corresponding data.
Table 8 and Table 9 provide a quick reference of available commands. This is followed by
a verbal description of each command. Two additional Truth Tables, Table 11 on
page 50, and Table 12 on page 52, appear following the Operation section, provide cur-
rent state/next state information.
10. All states and sequences not shown are illegal or reserved.
2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0
3. BA0-BA1 provide bank address and A0-A11 provide row address.
4. BA0-BA1 provide bank address; A0-Ai provide column address, (where i=8 for x16, i=9 for
5. A10 LOW: BA0-BA1 determine which bank is precharged.
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; for within the Self Refresh mode all
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and
9. DESELECT and NOP are functionally interchangeable.
select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combina-
tions of BA0-BA1 are reserved). A0-A11 provide the op-code to be written to the selected
mode register.
x8, and i = 9, 11 for x4) A10 HIGH enables the auto precharge feature (non persistent), and
A10 LOW disables the auto precharge feature.
A10 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”
inputs and I/Os are “Don’t Care” except for CKE.
should not be used) for read bursts with auto precharge enabled and for write bursts.
Name (Function)
Write Enable
Write Inhibit
21
CS#
H
L
L
L
L
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS#
DM
X
H
H
H
H
L
L
L
L
H
L
128Mb: x4, x8, x16 DDR SDRAM
CAS#
X
H
H
H
H
L
L
L
L
WE#
H
H
H
H
X
L
L
L
L
©2000 Micron Technology, Inc. All rights reserved.
Bank/Row
Bank/Col
Bank/Col
Op-Code
Addr
Code
Valid
DQ
X
X
X
X
X
Commands
Notes
6, 7
9
9
3
4
4
8
5
2