MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 42

IC DDR SDRAM 128MBIT 6NS 66TSOP

MT46V32M4TG-6T:D TR

Manufacturer Part Number
MT46V32M4TG-6T:D TR
Description
IC DDR SDRAM 128MBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT46V32M4TG-6T:D TR

Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
128M (32Mx4)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1024-2
Figure 26:
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE to READ - Interrupting
Bank a,
WRITE
Col b
T0
Notes: 1. DI b = data-in for column b, DO n = data-out for column n.
t
t
t
DQSS
DQSS
DQSS
2. An interrupted burst of 4 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 was used, DM and DQS would be required at T3 and T3n because the
DI
t
READ command would not mask these two data elements.
b
WTR is referenced from the first positive CK edge after the last data-in pair.
NOP
T1
DI
b
DI
b
T1n
NOP
T2
t
WTR
T2n
42
Bank a,
READ
Col n
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3n
DON’T CARE
CL = 2
CL = 2
CL = 2
T4
NOP
128Mb: x4, x8, x16 DDR SDRAM
TRANSITIONING DATA
T5
NOP
©2000 Micron Technology, Inc. All rights reserved.
DO
DO
DO
n
n
n
T5n
T6
NOP
Operations
T6n

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