W9864G6JH-6 Winbond Electronics, W9864G6JH-6 Datasheet
W9864G6JH-6
Specifications of W9864G6JH-6
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W9864G6JH-6 Summary of contents
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... Power Down Mode ....................................................................................................... 11 7.18 No Operation Command............................................................................................... 11 7.19 Deselect Command ...................................................................................................... 11 7.20 Clock Suspend Mode.................................................................................................... 11 8. OPERATION MODE ................................................................................................................. 12 9. ELECTRICAL CHARACTERISTICS......................................................................................... 13 9.1 Absolute Maximum Ratings .......................................................................................... 13 9.2 Recommended DC Operating Conditions .................................................................... 13 1M × 4 BANKS × 16 BITS SDRAM Publication Release Date: Aug. 31, 2010 - 1 - W9864G6JH Revision A02 ...
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... Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 39 11.20 Timing Chart of Burst Stop Cycle (Precharge Command).......................................... 39 11.21 CKE/DQM Input Timing (Write Cycle)......................................................................... 40 11.22 CKE/DQM Input Timing (Read Cycle)......................................................................... 41 12. PACKAGE SPECIFICATION .................................................................................................... 42 12.1 54L TSOP (II)-400 mil................................................................................................... 42 13. REVISION HISTORY ................................................................................................................ 43 Publication Release Date: Aug. 31, 2010 - 2 - W9864G6JH Revision A02 ...
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... GENERAL DESCRIPTION W9864G6JH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 1M words × 4 banks × 16 bits. W9864G6JH delivers a data bandwidth 200M words per second. For different application, W9864G6JH is sorted into the following speed grades: -5, -6/-6I, -7/- 7S. The -5 parts can run up to 200MHz/CL3. The -6/-6I parts can run up to 166MHz/CL3 (the -6I grade which is guaranteed to support -40° ...
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... AVAILABLE PART NUMBER PART NUMBER W9864G6JH-5 W9864G6JH-6 W9864G6JH-6I W9864G6JH-7 W9864G6JH-7S 4. PIN CONFIGURATION VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BS0 BS1 A10/ VDD SELF REFRESH SPEED CURRENT (MAX.) 200MHz/CL3 2 mA 166MHz/CL3 ...
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... Self Refresh mode is entered. Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Separated power from V immunity. Separated ground from V immunity. No connection W9864G6JH DESCRIPTION , to improve DQ noise improve DQ noise SS Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... COLUMN DECODER CELL ARRAY BANK #0 SENSE AMPLIFIER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER NOTE: The cell array configuration is 4096 * 256 * W9864G6JH COLUMN DECODER CELL ARRAY BANK #1 SENSE AMPLIFIER DQ0 DQ BUFFER DQ15 UDQM LDQM COLUMN DECODER CELL ARRAY ...
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... DDQ supplies. After power up, an initial pause of 200 µS is required DD ). The maximum time that each bank can be held active is RRD - 7 - W9864G6JH DD delay. WE pin voltage level RCD Publication Release Date: Aug. 31, 2010 Revision A02 + 0.3V RSC ) ...
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... Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. Publication Release Date: Aug. 31, 2010 - 8 - W9864G6JH Revision A02 ...
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... Data Data Data Data (disturb address is A0) No address carry from (disturb addresses are A0 and A1) No address carry from (disturb addresses are A0, A1 and A2) No address carry from ACCESS ADDRESS W9864G6JH BURST LENGTH BURST LENGTH Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode Data-in to Active delay (t DAL DAL (min). RAS - 10 - W9864G6JH ) has been satisfied. Issue of Auto- and When using the Auto Publication Release Date: Aug. 31, 2010 ...
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... The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. . The input buffers need (min (min.). CKS CK Publication Release Date: Aug. 31, 2010 - 11 - W9864G6JH ) of the REF Revision A02 ...
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... These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. CKEn-1 CKEn DQM BS0, 1 A10 ( ( ( ( ( ( W9864G6JH A0-A9, RAS CAS CS A11 ...
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... DDQ OPR T - OPR T -55 ~ 150 STG T SOLDER OUT SYM. MIN 3.0 DDQ V 2.7 DDQ V 2 -0.3 IL CAS CKE W9864G6JH UNIT NOTES V V °C °C °C 260 ° TYP. MAX. UNIT NOTES 3.3 3 3.6 V 3 0.8 V SYM. MIN. MAX. C 2.5 ...
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... SYM DD1 I 30 DD2 DD2P I 12 DD2S DD2PS DD3 DD3P I 80 DD4 I 65 DD5 I 2 DD6 SYMBOL MIN I( O( Publication Release Date: Aug. 31, 2010 - 14 - W9864G6JH = - ° MAX. UNIT NOTES -6/-6I -7/- MAX. UNIT NOTES 5 µA 5 µ 0.4 V Revision A02 ...
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... RCD CCD RRD 1000 7.5 1000 1000 6 1000 4 1.5 1 1.5 1 1.5 1.5 CKS CKH t 1.5 1.5 CMS CMH REF RSC XSR Publication Release Date: Aug. 31, 2010 - 15 - W9864G6JH = - ° -7/-7S UNIT NOTES MIN. MAX 100000 1000 7 1000 Revision A02 ...
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... Power up sequence please refer to "Functional Description" section described before Test Load diagram. output 7. t defines the time at which the outputs achieve the open circuit condition and is not referenced to HZ output level 1 ohms AC TEST LOAD - 16 - W9864G6JH 50 ohms 30pF Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... If tr & longer than 1nS, transient time compensation should be considered, i.e., [(tr + tf)/2-1]nS should be added to the parameter t ( The T maximum can’t be more than 10nS for low frequency application. ) 10. If clock rising time ( longer than 1nS 1nS. T /2-0.5)nS should be added to the parameter. T Publication Release Date: Aug. 31, 2010 - 17 - W9864G6JH (min.). IH (max.). ...
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... TIMING WAVEFORMS 10.1 Command Input Timing CLK RAS CAS WE A0-A11 BS0 CKS CKH CKE t t CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKS CKH CKS - 18 - W9864G6JH CMS tCMH t CKH Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... Read Timing CLK CS RAS CAS WE A0-A11 BS0,1 DQ Read Command Read CAS Latency Data-Out - 19 - W9864G6JH Valid Valid Data-Out Burst Length Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... Valid Data- CKS CKH CKS Valid Data- CMS CMH CMS Valid Valid Data-Out Data-Out CKS CKH CKS Valid Valid Data-Out Data-Out - 20 - W9864G6JH Valid Valid Data-in Data- Valid Valid Data-in Data- Valid Data-Out OPEN Valid Data-Out Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... Sequential Publication Release Date: Aug. 31, 2010 - 21 - W9864G6JH Burst Length Interleave Reserved Reserved Full Page Addressing Mode Sequential Interleave CAS Latency Reserved Reserved 2 3 Reserved Single Write Mode Burst read and Burst write Burst read and single write Revision A02 ...
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... RAS t t RCD RCD RBb RAc RBb CBx RAc t AC aw0 aw1 aw2 aw3 bx0 bx1 t RRD Active Precharge Precharge Active Read - 22 - W9864G6JH RAS RAS t RCD RBd CAy RBd CBz t AC bx3 bx2 cy0 cy1 cy2 cy3 t t RRD RRD Precharge ...
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... RAS t t RCD RCD RAc CBx RAc CAy t AC aw0 aw1 aw2 aw3 bx0 bx1 t RRD Active Read AP* Read AP the internal precharge start timing - 23 - W9864G6JH RAS RCD RBd RAe RBd CBz RAe bx2 bx3 cy0 cy1 cy2 cy3 t t RRD RRD ...
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... RAS RP t RAS t RCD RBb RBb CBy t AC ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 t RRD Precharge Active Read - 24 - W9864G6JH RCD RAc RAc CAz t AC by4 by5 by6 by7 CZ0 Active Read Precharge Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... RCD RBb CBy RBb t AC ax3 ax4 ax5 ax6 ax0 ax1 ax2 ax7 by0 t RRD AP* Read Active * AP is the internal precharge start timing - 25 - W9864G6JH RAS t t RAS RP t RCD RAc RAc CAz t AC by6 CZ0 by1 by4 by5 Active Read AP* Publication Release Date: Aug ...
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... Bank # RAS t RCD RBb RBb CBy ax4 ax5 ax6 by0 by1 by2 ax7 t RRD Precharge Active Write - 26 - W9864G6JH RAS t RCD RAc RAc CAz by3 by4 by5 by6 by7 CZ0 CZ1 Active Write Precharge Publication Release Date: Aug. 31, 2010 Revision A02 22 23 ...
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... RC t RAS t RCD RBb RBb CBy ax4 by0 by2 ax5 ax6 ax7 by1 by3 t RRD AP* Active Write * AP is the internal precharge start timing - 27 - W9864G6JH RAS t RCD RAb RAc CAz by5 by6 by7 by4 CZ0 CZ1 Active Write AP* Publication Release Date: Aug. 31, 2010 ...
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... CCD CCD t RAS t RAS t RCD CBx CAy CAm bx0 bx1 Ay0 Ay1 Read Read Read * AP is the internal precharge start timing - 28 - W9864G6JH CBz Ay2 am0 am1 am2 bz0 bz1 bz2 bz3 Precharge Read AP* Publication Release Date: Aug. 31, 2010 Revision A02 22 23 ...
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... BS0 BS1 t RCD A10 RAa A0-A9, RAa CAx A11 DQM CKE Bank #0 Active Read Bank #1 Bank #2 Idle Bank # RAS CAy ay0 ax0 ax1 ax2 ax3 ax4 ax5 Write - 29 - W9864G6JH ay1 ay2 ay3 ay4 Precharge Publication Release Date: Aug. 31, 2010 Revision A02 23 ...
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... CAw A11 DQM CKE Bank #0 Active Read Bank #1 Bank #2 Idle Bank # RCD RAb RAb aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing - 30 - W9864G6JH RAS CAx t AC bx0 bx1 bx2 bx3 Read AP* Publication Release Date: Aug. 31, 2010 Revision A02 23 ...
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... DQM CKE DQ aw0 aw1 Bank #0 Active Write Bank #1 Bank #2 Idle Bank # RCD RAb RAb CAx aw2 aw3 bx0 AP* Active Write * AP is the internal precharge start timing - 31 - W9864G6JH RAS RP RAc RAc bx1 bx2 bx3 AP* Active Publication Release Date: Aug. 31, 2010 Revision A02 23 ...
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... Auto Refresh Cycle CLK RAS CAS WE BS0,1 A10 A0-A9, A11 DQM CKE DQ All Banks Auto Prechage Refresh W9864G6JH Auto Refresh (Arbitrary Cycle) Publication Release Date: Aug. 31, 2010 Revision A02 23 ...
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... Self Refresh Cycle CLK RAS CAS WE BS0,1 A10 A0-A9, A11 DQM t SB CKE t CKS DQ All Banks Self Refresh Precharge Entry t CKS Self Refresh Cycle No Operation / Command Inhibit Self Refresh Exit Publication Release Date: Aug. 31, 2010 - 33 - W9864G6JH t XSR Arbitrary Cycle Revision A02 ...
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... RBa A0-A9, RBa CBv A11 DQM CKE Active Read Bank #0 Bank #1 Bank #2 Idle Bank # CBw CBx CBy av3 av0 av1 av2 aw0 ax0 ay0 Single Write - 34 - W9864G6JH CBz t AC az0 az1 az2 az3 Read Publication Release Date: Aug. 31, 2010 Revision A02 23 ...
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... When CKE goes high, command input must be No operation at next CLK rising edge. Violating refresh requirements during power-down may result in a loss of data CAa t CKS ax0 ax1 ax2 ax3 Read Precharge - 35 - W9864G6JH RAa RAa CAx CKS NOP Active Precharge Standby Power Down mode Publication Release Date: Aug ...
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... Act tRP AP Act tWR tRP AP tWR tRP represents the Write with Auto precharge command. represents the start of internal precharing. represents the Bank Active command W9864G6JH Act AP Act tWR tRP D7 Act AP Act Act tWR tRP D7 Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... Act Act Act Act Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. (min). RAS - 37 - W9864G6JH Act Act AP Act Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... Timing Chart of Write to Read Cycle In the case of Burst Length=4 0 (1) CAS Latency=2 Write ( a ) Command DQM DQ Write ( b ) Command DQM DQ (2) CAS Latency=3 Write ( a ) Command DQM DQ Write ( b ) Command DQM Write Write Write Read Read Read Read W9864G6JH Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... CAS latency =2 Read Command )CAS latency = 3 Read Command DQ (2) Write cycle Write Command Q0 DQ 11.20 Timing Chart of Burst Stop Cycle (Precharge Command ite rite BST BST BST Note: BST represents the Burst stop command W9864G6JH Publication Release Date: Aug. 31, 2010 Revision A02 1 1 ...
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... CKE/DQM Input Timing (Write Cycle) 1 CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM DQM MASK ( DQM MASK ( CKE MASK ( W9864G6JH CKE MASK CKE MASK Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... CKE/DQM Input Timing (Read Cycle) 1 CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM Open ( W9864G6JH Open Open Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... W9864G6JH MAX. 0.047 0.006 0.041 0.018 0.008 0.880 0.405 0.471 0.024 0.004 (*0.00315) Publication Release Date: Aug. 31, 2010 Revision A02 ...
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... Winbond for any damages resulting from such improper use or sales. PAGE All Initial formally data sheet 15 Revise -6I parts t RP Important Notice Publication Release Date: Aug. 31, 2010 - 43 - W9864G6JH DESCRIPTION and t value from 18nS to 15nS RCD Revision A02 ...