W9864G6JH-6 Winbond Electronics, W9864G6JH-6 Datasheet - Page 5

• Manufacturer Part Number: W9864G6JH-6
• Description: IC SDRAM 64MB 166MHZ 54TSOPII
• Manufacturer: Winbond Electronics

Specifications of W9864G6JH-6

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.3 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. PIN DESCRIPTION
23 ~ 26, 22,
PIN NUMBER
29 ~35
20, 21
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
45, 47, 48, 50,
51, 53
19
18
17
16
39, 15
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
A0−A11
BS0, BS1
DQ0−DQ15
UDQM
LDQM
CLK
CKE
V
V
V
V
NC
RAS
CS
CAS
WE
PIN NAME
DD
SS
DDQ
SSQ
Address
Bank Select
Data
Input/ Output
Chip Select
Row Address
Strobe
Column
Address Strobe Referred to RAS
Write Enable
Input/output
mask
Clock Inputs
Clock Enable
Power
Ground
Power for I/O
buffer
Ground for I/O
buffer
No Connection
FUNCTION
No connection.
Multiplexed pins for row and column address.
Row address: A0−A11. Column address: A0−A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock RAS , CAS and WE define the
operation to be executed.
Referred to RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside
DRAM.
Separated power from V
immunity.
Separated ground from V
immunity.
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Publication Release Date: Aug. 31, 2010
DESCRIPTION
DD
SS
, to improve DQ noise
, to improve DQ noise
W9864G6JH
Revision A02