CY7C1412AV18-167BZC Cypress Semiconductor Corp, CY7C1412AV18-167BZC Datasheet - Page 21

• Manufacturer Part Number: CY7C1412AV18-167BZC
• Description: IC SRAM 36MBIT 167MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1412AV18-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 36M (2M x 18)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q2668730

Document #: 38-05615 Rev. *C
Switching Characteristics
t
t
t
t
t
t
Set-up Times
t
t
t
t
Hold Times
t
t
t
t
Output Times
t
t
t
t
t
t
t
t
DLL Timing
t
t
t
Notes:
Parameter
23. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
24. t
25. At any given voltage and temperature t
26. This part has a voltage regulator internally; t
27. For D2 data signal on CY7C1425AV18 device, t
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
CO
DOH
CCQO
CQOH
CQD
CQDOH
CHZ
CLZ
KC Var
KC lock
KC Reset
Cypress
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
can be initiated.
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
Consortium
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CHQZ
CHQX1
KC Var
KC lock
KC Reset
Parameter
V
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge
to rising edge)
Address Set-up to K Clock Rise
Control Set-up to K Clock Rise (RPS, WPS)
Double Data Rate Control Set-up to Clock
(K, K) Rise (BWS
D
Address Hold after K Clock Rise
Control Hold after K Clock Rise (RPS, WPS)
Double Data Rate Control Hold after Clock
(K, K) Rise (BWS
D
C/C Clock Rise (or K/K in Single Clock Mode)
to Data Valid
Data Output Hold after Output C/C Clock Rise
(Active to Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Clock (C/C) Rise to High-Z
(Active to High-Z)
Clock (C/C) Rise to Low-Z
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
DD
[X:0]
[X:0]
(Typical) to the first Access
Set-up to Clock (K/K) Rise
Hold after Clock (K/K) Rise
CHZ
Over the Operating Range
is less than t
POWER
SD
Description
0
0
is 0.5 ns for 200 MHz, and 250 MHz frequencies.
[24,25]
is the time that the power needs to be supplied above V
, BWS
, BWS
CLZ
1
and t
1
, BWS
, BWS
[24,25]
CHZ
3
[26]
less than t
, BWS
3
, BWS
[22, 23]
4
)
CO
4
)
.
–0.30
–0.45
–0.45
–0.45
1024
Min.
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
4.0
1.6
1.6
1.8
0.0
30
1
–
–
–
–
–
250 MHz
Max.
0.45
0.45
0.30
0.45
0.20
6.3
1.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DD
–0.45
–0.45
–0.35
–0.45
minimum initially before a read or write operation
1024
Min.
5.0
2.0
2.0
2.2
0.0
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
30
200 MHz
1
–
–
–
–
–
Max.
0.45
0.45
0.35
0.45
0.20
7.9
2.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
–0.50
–0.40
–0.50
-0.50
1024
Min.
0.5
0.5
0.5
6.0
2.4
2.4
2.7
0.0
0.5
0.5
0.5
0.5
0.5
30
1
–
–
–
–
–
167 MHz
Page 21 of 25
Max.
0.50
0.50
0.40
0.50
0.20
8.4
2.7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
cycles
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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