ATXMEGA256A3-MU Atmel, ATXMEGA256A3-MU Datasheet - Page 105
ATXMEGA256A3-MU
Manufacturer Part Number
ATXMEGA256A3-MU
Description
8-bit Microcontrollers - MCU 8/16 bit 1.6V-3.6V 256KB + 8KB
Manufacturer
Atmel
Datasheet
1.ATXMEGA64A3-MU.pdf
(134 pages)
Specifications of ATXMEGA256A3-MU
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
AVR
Data Bus Width
8 bit/16 bit
Maximum Clock Frequency
32 MHz
Program Memory Size
256 KB
Data Ram Size
16 KB
On-chip Adc
Yes
Package / Case
QFN EP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
8
Data Rom Size
4 KB
Interface Type
I2C, SPI, USART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
50
Number Of Timers
7
Processor Series
ATXMega
Program Memory Type
Flash
Factory Pack Quantity
260
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.6 V
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8068T–AVR–12/10
22. Pending asynchronous RTC-interrupts will not wake up device
23. TWI Transmit collision flag not cleared on repeated start
24. Clearing TWI Stop Interrupt Flag may lock the bus
25. TWI START condition at bus timeout will cause transaction to be dropped
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
The TWI transmit collision flag should be automatically cleared on start and repeated start,
but is only cleared on start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the
hardware sets this flag due to a new address received, CLKHOLD is not cleared and the
SCL line is not released. This will lock the bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is
not IDLE, wait for the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
{
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
}
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
)
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
if ( !(COMMS_PORT.IN & PIN1_bm) )
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
break;
XMEGA A3
105
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