ATXMEGA256A3-MU Atmel, ATXMEGA256A3-MU Datasheet - Page 48

• Manufacturer Part Number: ATXMEGA256A3-MU
• Description: 8-bit Microcontrollers - MCU 8/16 bit 1.6V-3.6V 256KB + 8KB
• Manufacturer: Atmel

Specifications of ATXMEGA256A3-MU

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: AVR
• Data Bus Width: 8 bit/16 bit
• Maximum Clock Frequency: 32 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: QFN EP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: I2C, SPI, USART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 50
• Number Of Timers: 7
• Processor Series: ATXMega
• Program Memory Type: Flash
• Factory Pack Quantity: 260
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.6 V

29. Program and Debug Interfaces
29.1
29.2
29.3
29.3.1
29.3.2
8068T–AVR–12/10
Features
Overview
IEEE 1149.1 (JTAG) Boundary-scan
Boundary-scan Order
Boundary-scan Description Language Files
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The programming and debug facilities are accessed through the JTAG and PDI physical inter-
faces. The PDI physical interface uses one dedicated pin together with the Reset pin, and no
general purpose pins are used. JTAG uses four general purpose pins on PORTB.
The PDI is an Atmel proprietary protocol for communication between the microcontroller and
Atmel’s or third party development tools.
The JTAG physical layer handles the basic low-level serial communication over four I/O lines
named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and
boundary scan.
Table 30-8 on page 53
chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned
out. The scan order follows the pin-out order. Bit 4, 5, 6 and 7 of Port B is not in the scan chain,
since these pins constitute the TAP pins when the JTAG is enabled.
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description. BSDL files are available for
ATxmega256/192/128/64A3 devices.
See
PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)
JTAG Interface (IEEE std. 1149.1 compliant)
Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG)
Access to the OCD system
Programming of Flash, EEPROM, Fuses and Lock Bits
Table 30-8 on page 53
shows the Scan order between TDI and TDO when the Boundary-scan
for ATxmega256/192/128/64A3 Boundary Scan Order.
XMEGA A3
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