C8051F314R Silicon Labs, C8051F314R Datasheet

no-image

C8051F314R

Manufacturer Part Number
C8051F314R
Description
8-bit Microcontrollers - MCU 8KB 10ADC
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F314R

Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
8 KB
Data Ram Size
1.25 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
LQFP-32
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
17
Data Rom Size
128 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
29
Number Of Timers
5
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Rev. 1.7 8/06
Analog Peripherals
-
-
On-Chip Debug
-
-
-
-
Supply Voltage 2.7 to 3.6 V
-
-
-
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
10-Bit ADC (C8051F310/1/2/3/6 only)
Comparators
On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug 
(no emulator required)
Provides breakpoints, single stepping, 
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-Chips, target pods, and sockets
Complete development kit
Typical operating current:
Typical stop mode current:
Temperature range:
Up to 200 ksps
Up to 21, 17, or 13 external single-ended or differen-
tial inputs
VREF from external pin or V
Built-in temperature sensor
External conversion start input
Programmable hysteresis and response time
Configurable as interrupt or reset source
(Comparator0)
Low current ( 0.5 µA)
C8051F310/1/2/3/6 only
SENSOR
M
U
INTERRUPTS
A
X
TEMP
ISP FLASH
16 kB/8 kB
PROGRAMMABLE PRECISION INTERNAL
5 mA at 25 MHz;
–40 to +85 °C
11 µA at 32 kHz
0.1 µA
DD
PERIPHERALS
200ksps
HIGH-SPEED CONTROLLER CORE
14
Copyright © 2006 by Silicon Laboratories
ANALOG
10-bit
ADC
COMPARATORS
+
-
OSCILLATOR
CIRCUITRY
+
-
VOLTAGE
8051 CPU
(25MIPS)
DEBUG
High Speed 8051 µC Core
-
-
-
Memory
-
-
Digital Peripherals
-
-
-
-
-
Clock Sources
-
-
-
Packages
-
-
-
C8051F310/1/2/3/4/5/6/7
Timer 0
Timer 1
Timer 2
Timer 3
SMBus
UART
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
1280 bytes internal data RAM (1024 + 256)
16 kB (C8051F310/1/6/7) or 8 kB (C8051F312/3/4/5)
Flash; In-system programmable in 512-byte sectors
29/25/21 Port I/O; 
All 5 V tolerant with high sink current
Hardware enhanced UART, SMBus™, and SPI™
serial ports
Four general purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with five
capture/compare modules
Real time clock capability using PCA or timer and 
external clock source
Internal oscillator: 24.5 MHz with ±2% accuracy
supports crystal-less UART operation
External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
Can switch between clock sources on-the-fly; useful
in power saving modes
32-pin LQFP (C8051F310/2/4)
28-pin QFN (C8051F311/3/5)
24-pin QFN (C8051F316/7)
PCA
SPI
DIGITAL I/O
POR
8/16 kB ISP Flash MCU Family
1280 B
SRAM
Port 0
Port 1
Port 2
Port 3
WDT
C8051F31x

C8051F314R Summary of contents

Page 1

Analog Peripherals - 10-Bit ADC (C8051F310/1/2/3/6 only 200 ksps • 21, 17 external single-ended or differen- • tial inputs VREF from external pin or V • Built-in temperature sensor • External conversion start input ...

Page 2

C8051F310/1/2/3/4/5/6 OTES 2 Rev. 1.7 ...

Page 3

Table Of Contents 1. System Overview.................................................................................................... 17 1.1. CIP-51™ Microcontroller Core.......................................................................... 27 1.1.1. Fully 8051 Compatible.............................................................................. 27 1.1.2. Improved Throughput ............................................................................... 27 1.1.3. Additional Features .................................................................................. 28 1.2. On-Chip Memory............................................................................................... 29 1.3. On-Chip Debug Circuitry................................................................................... 30 1.4. Programmable Digital I/O ...

Page 4

C8051F310/1/2/3/4/5/6/7 8.3.4. Interrupt Latency ...................................................................................... 95 8.3.5. Interrupt Register Descriptions................................................................. 97 8.4. Power Management Modes ............................................................................ 102 8.4.1. Idle Mode................................................................................................ 102 8.4.2. Stop Mode .............................................................................................. 103 9. Reset Sources....................................................................................................... 105 9.1. Power-On Reset ............................................................................................. 106 9.2. Power-Fail Reset / V ...

Page 5

SMBus............................................................................................ 149 14.4.1.SMBus Configuration Register............................................................... 150 14.4.2.SMB0CN Control Register ..................................................................... 153 14.4.3.Data Register ......................................................................................... 156 14.5.SMBus Transfer Modes.................................................................................. 157 14.5.1.Master Transmitter Mode ....................................................................... 157 14.5.2.Master Receiver Mode ........................................................................... 158 14.5.3.Slave Receiver Mode ............................................................................. 159 14.5.4.Slave Transmitter Mode ......................................................................... ...

Page 6

C8051F310/1/2/3/4/5/6/7 18.2.3.High-Speed Output Mode ...................................................................... 208 18.2.4.Frequency Output Mode ........................................................................ 209 18.2.5.8-Bit Pulse Width Modulator Mode......................................................... 210 18.2.6.16-Bit Pulse Width Modulator Mode....................................................... 211 18.3.Watchdog Timer Mode ................................................................................... 212 18.3.1.Watchdog Timer Operation .................................................................... 212 18.3.2.Watchdog Timer Usage ......................................................................... 213 18.4.Register Descriptions ...

Page 7

List of Figures 1. System Overview Figure 1.1. C8051F310 Block Diagram .................................................................... 19 Figure 1.2. C8051F311 Block Diagram .................................................................... 20 Figure 1.3. C8051F312 Block Diagram .................................................................... 21 Figure 1.4. C8051F313 Block Diagram .................................................................... 22 Figure 1.5. C8051F314 Block Diagram .................................................................... ...

Page 8

C8051F310/1/2/3/4/5/6/7 7. Comparators Figure 7.1. Comparator0 Functional Block Diagram ................................................ 69 Figure 7.2. Comparator1 Functional Block Diagram ................................................ 70 Figure 7.3. Comparator Hysteresis Plot ................................................................... 71 8. CIP-51 Microcontroller Figure 8.1. CIP-51 Block Diagram............................................................................ 79 Figure 8.2. Memory Map .......................................................................................... ...

Page 9

Figure 16.8. SPI Master Timing (CKPHA = 0)........................................................ 183 Figure 16.9. SPI Master Timing (CKPHA = 1)........................................................ 183 Figure 16.10. SPI Slave Timing (CKPHA = 0)........................................................ 184 Figure 16.11. SPI Slave Timing (CKPHA = 1)........................................................ 184 17. Timers Figure 17.1. ...

Page 10

C8051F310/1/2/3/4/5/6 OTES 10 Rev. 1.7 ...

Page 11

List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 18 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings .................................................................... 35 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics ....................................................... 36 Table 3.2. Electrical ...

Page 12

C8051F310/1/2/3/4/5/6/7 15. UART0 Table 15.1. Timer Settings for Standard Baud Rates  Using the Internal Oscillator ............................................................... 170 Table 15.2. Timer Settings for Standard Baud Rates  Using an External 25 MHz Oscillator .................................................. 170 Table 15.3. Timer Settings for ...

Page 13

List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 57 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . ...

Page 14

C8051F310/1/2/3/4/5/6/7 SFR Definition 13.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 137 SFR Definition 13.6. P0SKIP: Port0 Skip ...

Page 15

SFR Definition 18.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 219 C2 Register Definition 20.1. C2ADD: C2 Address . . . . . . . . . ...

Page 16

C8051F310/1/2/3/4/5/6 OTES 16 Rev. 1.7 ...

Page 17

... The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands ...

Page 18

C8051F310/1/2/3/4/5/6/7 Table 1.1. Product Selection Guide C8051F310 25 16 1280 C8051F310- 1280 C8051F311 25 16 1280 C8051F311- 1280 C8051F312 25 8 1280 C8051F312- 1280 C8051F313 25 8 1280 C8051F313- 1280 C8051F314 25 ...

Page 19

Analog/Digital Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.1. C8051F310 Block Diagram C8051F310/1/2/3/4/5/6/7 Port 0 Latch Port 1 Latch UART 8 16kbyte Timer FLASH 0 ...

Page 20

C8051F310/1/2/3/4/5/6/7 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.2. C8051F311 Block Diagram 20 Port 0 Latch Port 1 Latch UART 8 16kbyte Timer FLASH 0 ...

Page 21

Analog/Digital Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.3. C8051F312 Block Diagram C8051F310/1/2/3/4/5/6/7 Port 0 Latch Port 1 Latch UART Timer FLASH ...

Page 22

C8051F310/1/2/3/4/5/6/7 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.4. C8051F313 Block Diagram 22 Port 0 Latch Port 1 Latch UART Timer FLASH ...

Page 23

Analog/Digital Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.5. C8051F314 Block Diagram C8051F310/1/2/3/4/5/6/7 Port 0 Latch Port 1 Latch UART Timer FLASH ...

Page 24

C8051F310/1/2/3/4/5/6/7 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.6. C8051F315 Block Diagram 24 Port 0 Latch Port 1 Latch UART Timer FLASH ...

Page 25

Analog/Digital Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.7. C8051F316 Block Diagram C8051F310/1/2/3/4/5/6/7 Port 0 Latch Port 1 Latch UART Timer FLASH ...

Page 26

C8051F310/1/2/3/4/5/6/7 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.8. C8051F317 Block Diagram 26 Port 0 Latch Port 1 Latch UART Timer FLASH ...

Page 27

... With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.9 shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum sys- tem clocks Silicon Labs (25 MHz clk) Figure 1.9. Comparison of Peak MCU Execution Speeds C8051F310/1/2/3/4/5/6/7 2 2/3 3 3/4 ...

Page 28

C8051F310/1/2/3/4/5/6/7 1.1.3. Additional Features The C8051F31x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 14 interrupt sources into the CIP-51 (as ...

Page 29

On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct ...

Page 30

... The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the precision analog peripherals. ...

Page 31

Programmable Digital I/O and Crossbar C8051F310/2/4 devices include 29 I/O pins (three byte-wide Ports and one 5-bit-wide Port); C8051F311/3/5 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F316/7 devices include 21 I/O pins (one byte-wide ...

Page 32

C8051F310/1/2/3/4/5/6/7 1.5. Serial Ports The C8051F31x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the ...

Page 33

Analog to Digital Converter The C8051F310/1/2/3/6 devices include an on-chip 10-bit SAR ADC with a 25-channel differential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit accuracy with an INL of ±1LSB. The ...

Page 34

C8051F310/1/2/3/4/5/6/7 1.8. Comparators C8051F31x devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port ...

Page 35

Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or RST with respect to GND Voltage on V with respect to GND DD Maximum Total current through ...

Page 36

C8051F310/1/2/3/4/5/6/7 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40°C to +85°C, 25 MHz System Clock unless otherwise specified. Parameter Digital Supply Voltage Digital Supply RAM Data Retention Voltage Specified Operating Temperature Range SYSCLK (system clock frequency) ...

Page 37

Table 3.1. Global DC Electrical Characteristics (Continued) –40°C to +85°C, 25 MHz System Clock unless otherwise specified. Parameter Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) I (Note Supply Sensitivity (Note 3, DD Note ...

Page 38

C8051F310/1/2/3/4/5/6/7 Other electrical characteristics tables are found in the data sheet section corresponding to the associated peripherals. For more information on electrical characteristics for a specific peripheral, refer to the page indicated in Table 3.2. Table 3.2. Electrical Characteristics Quick ...

Page 39

Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F31x Pin Numbers Name ‘F310/2/4 ‘F311/3/5 ‘F316 GND 3 3 RST C2CK P3. C2D P0. VREF P0 ...

Page 40

C8051F310/1/2/3/4/5/6/7 Table 4.1. Pin Definitions for the C8051F31x (Continued) Pin Numbers Name ‘F310/2/4 ‘F311/3/5 ‘F316 P2.5 ...

Page 41

P0 P0.0 3 GND VDD 4 5 /RST/C2CK P3.0/C2D 6 P3 P3.2 Figure 4.1. LQFP-32 Pinout Diagram (Top View) C8051F310/1/2/3/4/5/6/7 C8051F310/2/4 Top View Rev. 1.7 24 P1.2 23 P1.3 22 P1.4 21 P1.5 20 P1.6 19 ...

Page 42

C8051F310/1/2/3/4/5/6 PIN 1 IDENTIFIER Figure 4.2. LQFP-32 Package Diagram 42 Table 4.2. LQFP-32 Package Dimensions MIN 0.05 A2 1. ...

Page 43

GND P0.1 1 P0.0 2 GND 3 C8051F311/3/5 VDD 4 /RST/C2CK 5 P3.0/C2D 6 P2.7 7 Figure 4.3. QFN-28 Pinout Diagram (Top View) C8051F310/1/2/3/4/5/6/7 Top View GND Rev. 1.7 21 P1.1 20 P1.2 19 P1.3 18 P1.4 17 P1.5 16 ...

Page 44

C8051F310/1/2/3/4/5/6/7 Bottom View DETAIL Side View DETAIL 1 Figure 4.4. QFN-28 Package Drawing ...

Page 45

Optional GND Connection L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.5. Typical QFN-28 Landing Diagram C8051F310/1/2/3/4/5/6/7 Top View E2 E Rev. 1.7 0. ...

Page 46

C8051F310/1/2/3/4/5/6/7 0.50 mm 0.60 mm 0. 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.6. QFN-28 Solder Paste Recommendation 46 Top View 0.60 mm 0.30 mm 0. ...

Page 47

P0.1 1 P0.0 2 GND 3 VDD 4 /RST / C2CK 5 P3.0 / C2D 6 Figure 4.7. QFN-24 Pinout Diagram (Top View) C8051F310/1/2/3/4/5/6/7 C8051F316/7 Top View GND Rev. 1.7 18 P1.0 17 P1.1 16 P1.2 15 P1.3 14 P1.4 ...

Page 48

C8051F310/1/2/3/4/5/6/7 Bottom View Side View e Figure 4.8. QFN-24 Package Drawing 48 Table 4.4. QFN-24 Package Dimensions ...

Page 49

Pin #1 Optional GND Connection 0.20 mm 0.30 mm 0.35 mm 0.45 mm 0.75 mm 0.10 mm Figure 4.9. Typical QFN-24 Landing Diagram C8051F310/1/2/3/4/5/6/7 Top View E2 E Rev. 1.7 49 ...

Page 50

C8051F310/1/2/3/4/5/6/7 Pin #1 0.80 mm 0.20 mm 0.30 mm 0.35 mm 0.45 mm 0.75 mm 0.10 mm Figure 4.10. QFN-24 Solder Paste Recommendation 50 Top View 0.60 mm 0.45 mm 0.30 mm 0.20 mm 0. ...

Page 51

ADC (ADC0, C8051F310/1/2/3/6 only) The ADC0 subsystem for the C8051F310/1/2/3/6 consists of two analog multiplexers (referred to collec- tively as AMUX0) with 25 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable ...

Page 52

C8051F310/1/2/3/4/5/6/7 Inputs are measured from ‘0’ to VREF * 1023/1024. Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’. Input Voltage Right-Justified ADC0H:ADC0L VREF x 1023/1024 ...

Page 53

The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea- surements (see Table 5.1 for linearity specifications). For absolute temperature measurements, gain and/ or offset calibration is recommended. Typically a 1-point calibration includes the following steps: ...

Page 54

C8051F310/1/2/3/4/5/6/7 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC ...

Page 55

Tracking Modes According to Table 5.1, each ADC0 conversion must be preceded by a minimum tracking time for the con- verted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default ...

Page 56

C8051F310/1/2/3/4/5/6/7 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 ...

Page 57

SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0P4–0: AMUX0 Positive Input Selection AMX0P4–0 00000 00001 00010 00011 00100 00101 00110 ...

Page 58

C8051F310/1/2/3/4/5/6/7 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection. Note that when GND is selected as ...

Page 59

SFR Definition 5.3. ADC0CF: ADC0 Configuration R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the ...

Page 60

C8051F310/1/2/3/4/5/6/7 SFR Definition 5.6. ADC0CN: ADC0 Control R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is ...

Page 61

Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space ...

Page 62

C8051F310/1/2/3/4/5/6/7 SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: ...

Page 63

Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF x ...

Page 64

C8051F310/1/2/3/4/5/6/7 5.4.2. Window Detector In Differential Mode Figure 5.8 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between ...

Page 65

Table 5.1. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic Performance ...

Page 66

C8051F310/1/2/3/4/5/6 OTES 66 Rev. 1.7 ...

Page 67

Voltage Reference (C8051F310/1/2/3/6 only) The voltage reference MUX on C8051F310/1/2/3/6 devices is configurable to use an externally connected voltage reference, or the power supply voltage (see Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the ...

Page 68

C8051F310/1/2/3/4/5/6/7 SFR Definition 6.1. REF0CN: Reference Control R/W R/W R/W Bit7 Bit6 Bit5 Bits7–4: UNUSED. Read = 0000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF input ...

Page 69

Comparators C8051F31x devices include two on-chip programmable voltage comparators: Comparator0 is shown in Figure 7.1; Comparator1 is shown in Figure 7.2. The two comparators operate identically with the following exceptions: (1) Their input selections differ as shown in Figure ...

Page 70

C8051F310/1/2/3/4/5/6/7 The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous ...

Page 71

CP0+ VIN+ CP0- VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN+ OUTPUT V OL Positive Hysteresis Disabled Figure 7.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN (for n ...

Page 72

C8051F310/1/2/3/4/5/6/7 SFR Definition 7.1. CPT0CN: Comparator0 Control R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: ...

Page 73

SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection R/W R/W R CMX0N1 CMX0N0 Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bits5–4: CMX0N1–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is ...

Page 74

C8051F310/1/2/3/4/5/6/7 SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection R/W R/W R CP0RIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator Rising-Edge Interrupt Enable. 0: Comparator rising-edge interrupt disabled. 1: Comparator rising-edge ...

Page 75

SFR Definition 7.4. CPT1CN: Comparator1 Control R/W R R/W CP1EN CP1OUT CP1RIF Bit7 Bit6 Bit5 Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1–. 1: Voltage ...

Page 76

C8051F310/1/2/3/4/5/6/7 SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection R/W R/W R CMX1N1 CMX1N0 Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bits5–4: CMX1N1–CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin ...

Page 77

SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection R/W R/W R CP1RIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP1RIE: Comparator Rising-Edge Interrupt Enable. 0: Comparator rising-edge interrupt disabled 1: Comparator rising-edge interrupt ...

Page 78

C8051F310/1/2/3/4/5/6/7 Table 7.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. Parameter Response Time: 1 Mode 0, Vcm = 1.5 V Response ...

Page 79

CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...

Page 80

... This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. C2 details can be found in The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro- vides an integrated development environment (IDE) including an editor, evaluation compiler, assembler, debugger and programmer ...

Page 81

CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 8.1.2. MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F31x does ...

Page 82

C8051F310/1/2/3/4/5/6/7 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ORL A, direct OR direct byte to A ORL A, @Ri OR indirect RAM to A ORL A, #data OR immediate to A ORL direct direct ...

Page 83

Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description XCH A, @Ri Exchange indirect RAM with A XCHD A, @Ri Exchange low nibble of indirect RAM with A CLR C Clear Carry CLR bit Clear direct bit SETB C Set ...

Page 84

C8051F310/1/2/3/4/5/6/7 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first ...

Page 85

Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but ...

Page 86

C8051F310/1/2/3/4/5/6/7 8.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. ...

Page 87

Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a ...

Page 88

C8051F310/1/2/3/4/5/6/7 Table 8.3. Special Function Registers Register Address Description SFRs are listed in alphabetical order. All undefined SFR locations are reserved ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ...

Page 89

Table 8.3. Special Function Registers (Continued) Register Address Description P2SKIP 0xD6 Port 2 Skip P3 0xB0 Port 3 Latch P3MDIN 0xF4 Port 3 Input Mode Configuration P3MDOUT 0xA7 Port 3 Output Mode Configuration PCA0CN 0xD8 PCA Control PCA0CPH0 0xFC PCA ...

Page 90

C8051F310/1/2/3/4/5/6/7 Table 8.3. Special Function Registers (Continued) Register Address Description TMR2L 0xCC Timer/Counter 2 Low TMR2RLH 0xCB Timer/Counter 2 Reload High TMR2RLL 0xCA Timer/Counter 2 Reload Low TMR3CN 0x91 Timer/Counter 3Control TMR3H 0x95 Timer/Counter 3 High TMR3L 0x94 Timer/Counter 3Low ...

Page 91

SFR Definition 8.2. DPH: Data Pointer High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed Flash memory. SFR ...

Page 92

C8051F310/1/2/3/4/5/6/7 SFR Definition 8.4. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction). It ...

Page 93

SFR Definition 8.6. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7– Register. This register serves as a second accumulator for certain arithmetic operations. 8.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total ...

Page 94

C8051F310/1/2/3/4/5/6/7 instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. 8.3.1. MCU Interrupt Sources and Vectors The MCUs support 14 interrupt sources. Software can simulate an ...

Page 95

External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active ...

Page 96

C8051F310/1/2/3/4/5/6/7 Table 8.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 (/INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (/INT1) 0x0013 Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B RESERVED ...

Page 97

Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the ...

Page 98

C8051F310/1/2/3/4/5/6/7 SFR Definition 8.8. IP: Interrupt Priority R/W R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of ...

Page 99

SFR Definition 8.9. EIE1: Extended Interrupt Enable 1 R/W R/W R/W ET3 ECP1 ECP0 Bit7 Bit6 Bit5 Bit7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable ...

Page 100

C8051F310/1/2/3/4/5/6/7 SFR Definition 8.10. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PT3 PCP1 PCP0 Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set ...

Page 101

SFR Definition 8.11. IT01CF: INT0/INT1 Configuration R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to SFR Definition 17.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 ...

Page 102

C8051F310/1/2/3/4/5/6/7 8.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts ...

Page 103

Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripher- ...

Page 104

C8051F310/1/2/3/4/5/6 OTES 104 Rev. 1.7 ...

Page 105

Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...

Page 106

C8051F310/1/2/3/4/5/6/7 9.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until additional delay occurs before the device is released from reset; the delay decreases as ...

Page 107

For example, if the V V monitor will still be enabled after the reset. DD Important Note: The V monitor must be enabled before it is selected as a reset source. Selecting the DD V monitor ...

Page 108

C8051F310/1/2/3/4/5/6/7 9.4. Missing Clock Detector Reset The Missing Clock Detector (MCD one-shot circuit that is triggered by the system clock. If the system clock remains high or low for more than 100 µs, the one-shot will time out ...

Page 109

SFR Definition 9.2. RSTSRC: Reset Source R R R/W - FERROR C0RSEF Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bit6: FERROR: Flash Error Indicator. 0: Source of last reset was not a Flash read/write/erase error. ...

Page 110

C8051F310/1/2/3/4/5/6/7 Table 9.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter I RST Output Low Voltage OL RST Input High Voltage RST Input Low Voltage RST = 0.0 V RST Input Pullup Current V Monitor Threshold (V ...

Page 111

... Programming The Flash Memory The simplest means of programming the Flash memory is through the C2 interface using programming tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial- ized device. For details on the C2 commands to program Flash memory, see on page 223 ...

Page 112

C8051F310/1/2/3/4/5/6/7 10.1.3. Flash Write Procedure Flash bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte Flash page containing the target location, as described in 10.1.2. Step 3. Set the PSWE ...

Page 113

Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in ...

Page 114

C8051F310/1/2/3/4/5/6/7 The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware ...

Page 115

Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating ...

Page 116

C8051F310/1/2/3/4/5/6/7 10. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your compiler documentation for instructions regarding how to explicitly locate variables in dif- ferent memory areas. 11. Add address bounds checking to ...

Page 117

SFR Definition 10.2. FLKEY: Flash Lock and Key R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: FLKEY: Flash Lock and Key Register Write: This register must be written to before Flash writes or erases can be performed. Flash remains locked until ...

Page 118

C8051F310/1/2/3/4/5/6 OTES 118 Rev. 1.7 ...

Page 119

External RAM The C8051F31x devices include 1024 bytes of RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX ...

Page 120

C8051F310/1/2/3/4/5/6 OTES 120 Rev. 1.7 ...

Page 121

Oscillators C8051F31x devices include a programmable internal oscillator and an external oscillator drive circuit. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 12.1. The system clock can be sourced ...

Page 122

C8051F310/1/2/3/4/5/6/7 SFR Definition 12.1. OSCICL: Internal Oscillator Calibration R/W R/W R/W Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bits 6–0: OSCICL: Internal Oscillator Calibration Register. This register determines the internal oscillator period. This reset value ...

Page 123

SFR Definition 12.3. CLKSEL: Clock Select R/W R/W R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved CLKSL0 00000000 Bit7 Bit6 Bit5 Bits7–1: Reserved. Read = 0000000b, Must Write = 0000000. Bit0: CLKSL0: System Clock Source Select Bit. 0: SYSCLK derived ...

Page 124

C8051F310/1/2/3/4/5/6/7 12.2. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator ...

Page 125

SFR Definition 12.4. OSCXCN: External Oscillator Control R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal ...

Page 126

C8051F310/1/2/3/4/5/6/7 12.4. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 12.1, Option 1. The External Oscillator Frequency Control value (XFCN) ...

Page 127

External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 12.1, Option 2. The capacitor should be no greater than 100 pF; however, ...

Page 128

C8051F310/1/2/3/4/5/6 OTES 128 Rev. 1.7 ...

Page 129

Port Input/Output Digital and analog resources are available through 29 I/O pins (C8051F310/2/4 I/O pins (C8051F311/3/5 I/O pins (C8051F316/7). Port pins are organized as three byte-wide Ports and one 5-bit-wide (C8051F310/2/4) or 1-bit-wide (C8051F311/3/5) Port. ...

Page 130

C8051F310/1/2/3/4/5/6/7 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT ANALOG INPUT PORT-INPUT Figure 13.2. Port I/O Cell Block Diagram 130 VDD GND Analog Select Rev. 1.7 VDD (WEAK) PORT PAD ...

Page 131

Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 13.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding ...

Page 132

C8051F310/1/2/3/4/5/6 Signals PIN I TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI P0SKIP[0:7] ...

Page 133

... Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. ...

Page 134

C8051F310/1/2/3/4/5/6/7 SFR Definition 13.1. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W CP1AE CP1E CP0AE Bit7 Bit6 Bit5 Bit7: CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. Bit6: ...

Page 135

SFR Definition 13.2. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W WEAKPUD XBARE T1E Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for Ports whose I/O are configured as analog input). 1: ...

Page 136

C8051F310/1/2/3/4/5/6/7 SFR Definition 13.3. P0: Port0 R/W R/W R/W P0.7 P0.6 P0.5 Bit7 Bit6 Bit5 Bits7–0: P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P0MDOUT.n ...

Page 137

SFR Definition 13.5. P0MDOUT: Port0 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n ...

Page 138

C8051F310/1/2/3/4/5/6/7 SFR Definition 13.7. P1: Port1 R/W R/W R/W P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits7–0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n ...

Page 139

SFR Definition 13.9. P1MDOUT: Port1 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in regis- ter P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n ...

Page 140

C8051F310/1/2/3/4/5/6/7 SFR Definition 13.11. P2: Port2 R/W R/W R/W P2.7 P2.6 P2.5 Bit7 Bit6 Bit5 Bits7–0: P2.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P2MDOUT.n ...

Page 141

SFR Definition 13.13. P2MDOUT: Port2 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P2.7–P2.0 (respectively): ignored if corresponding bit in regis- ter P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n ...

Page 142

C8051F310/1/2/3/4/5/6/7 SFR Definition 13.15. P3: Port3 R/W R/W R/W P3.7 P3.6 P3.5 Bit7 Bit6 Bit5 Bits7–0: P3.[7:0] Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0). ...

Page 143

SFR Definition 13.17. P3MDOUT: Port3 Output Mode R/W R/W R Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write - don’t care. Bits4–0: Output Configuration Bits for P3.4–P3.0 (respectively): ignored if corresponding bit in regis- ter P3MDIN ...

Page 144

C8051F310/1/2/3/4/5/6 OTES 144 Rev. 1.7 ...

Page 145

SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system ...

Page 146

C8051F310/1/2/3/4/5/6/7 14.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: • The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. • The I2C-Bus Specification—Version 2.0, Philips Semiconductor. • ...

Page 147

The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated ...

Page 148

C8051F310/1/2/3/4/5/6/7 14.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave ...

Page 149

Using the SMBus The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con- trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent ...

Page 150

C8051F310/1/2/3/4/5/6/7 14.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the ...

Page 151

Figure 14.4 shows the typical SCL generation described by Equation 14.2. Notice that T twice as large The actual SCL output may vary due to other devices on the bus (SCL may be LOW extended low by ...

Page 152

C8051F310/1/2/3/4/5/6/7 SFR Definition 14.1. SMB0CF: SMBus Clock/Configuration R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus ...

Page 153

SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 14.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to ...

Page 154

C8051F310/1/2/3/4/5/6/7 SFR Definition 14.2. SMB0CN: SMBus Control R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: ...

Page 155

Table 14.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When... • A START is generated. MASTER • START is generated. • SMB0DAT is written before the start of an TXMODE SMBus frame. • A START followed by ...

Page 156

C8051F310/1/2/3/4/5/6/7 14.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...

Page 157

SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. ...

Page 158

C8051F310/1/2/3/4/5/6/7 14.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the ...

Page 159

Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and ...

Page 160

C8051F310/1/2/3/4/5/6/7 14.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START ...

Page 161

SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown response ...

Page 162

C8051F310/1/2/3/4/5/6/7 Table 14.4. SMBus Status Decoding (Continued) Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A Slave byte was transmitted ...

Page 163

UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “15.1. ...

Page 164

C8051F310/1/2/3/4/5/6/7 15.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer ...

Page 165

Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 15.3. Figure 15.3. UART Interconnect Diagram 15.2.1. 8-Bit UART ...

Page 166

C8051F310/1/2/3/4/5/6/7 15.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit ...

Page 167

Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it ...

Page 168

C8051F310/1/2/3/4/5/6/7 SFR Definition 15.1. SCON0: Serial Port 0 Control R/W R R/W S0MODE MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit ...

Page 169

SFR Definition 15.2. SBUF0: Serial (UART0) Port Data Buffer R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB–LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is ...

Page 170

C8051F310/1/2/3/4/5/6/7 Table 15.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% *Note: SCA1–SCA0 and ...

Page 171

Table 15.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator Frequency: 22.1184 MHz Target Baud Rate Oscilla- Baud Rate % Error tor Divide (bps) Factor 230400 0.00% 96 115200 0.00% 192 57600 0.00% 384 28800 0.00% ...

Page 172

C8051F310/1/2/3/4/5/6/7 Table 15.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 ...

Page 173

Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple ...

Page 174

C8051F310/1/2/3/4/5/6/7 16.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 16.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave ...

Page 175

SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data ...

Page 176

C8051F310/1/2/3/4/5/6/7 Master Device 1 Figure 16.2. Multiple-Master Mode Connection Diagram Master Device Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram Master Device GPIO Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram 176 NSS GPIO MISO MISO ...

Page 177

SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave slave, bytes are shifted in through the MOSI pin and out through the MISO pin by ...

Page 178

C8051F310/1/2/3/4/5/6/7 16.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to ...

Page 179

SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB Bit 6 MISO MSB Bit 6 NSS (4-Wire Mode) Figure 16.6. Slave Mode Data/Clock Timing (CKPHA = 0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure ...

Page 180

C8051F310/1/2/3/4/5/6/7 16.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related ...

Page 181

SFR Definition 16.2. SPI0CN: SPI0 Control R/W R/W R/W SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 Bit7 Bit6 Bit5 Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. ...

Page 182

C8051F310/1/2/3/4/5/6/7 SFR Definition 16.3. SPI0CKR: SPI0 Clock Rate R/W R/W R/W SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits 7–0: SCR7–SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master ...

Page 183

SCK* T MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 16.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is ...

Page 184

C8051F310/1/2/3/4/5/6/7 NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 16.10. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* ...

Page 185

Table 16.1. SPI Slave Timing Parameters Parameter Description Master Mode Timing* (See Figure 16.8 and Figure 16.9) T SCK High Time MCKH T SCK Low Time MCKL T MISO Valid to SCK Shift Edge MIS T SCK Shift Edge to ...

Page 186

C8051F310/1/2/3/4/5/6 OTES 186 Rev. 1.7 ...

Page 187

Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can be ...

Page 188

C8051F310/1/2/3/4/5/6/7 The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to “13.1. Priority Crossbar Decoder” on page 131 ...

Page 189

Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun- ter/timers are enabled and configured in Mode 1 in the same manner as for Mode ...

Page 190

C8051F310/1/2/3/4/5/6/7 17.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits ...

Page 191

SFR Definition 17.1. TCON: Timer Control R/W R/W R/W TF1 TR1 TF0 Bit7 Bit6 Bit5 Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto- matically cleared ...

Page 192

C8051F310/1/2/3/4/5/6/7 SFR Definition 17.2. TMOD: Timer Mode R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only ...

Page 193

SFR Definition 17.3. CKCON: Clock Control R/W R/W R/W T3MH T3ML T2MH Bit7 Bit6 Bit5 Bit7: T3MH: Timer 3 High Byte Clock Select. This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured ...

Page 194

C8051F310/1/2/3/4/5/6/7 SFR Definition 17.4. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 17.5. TL1: Timer 1 ...

Page 195

Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the ...

Page 196

C8051F310/1/2/3/4/5/6/7 17.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 17.5. TMR2RLL holds the reload value for TMR2L; ...

Page 197

SFR Definition 17.8. TMR2CN: Timer 2 Control R/W R/W R/W TF2H TF2L TF2LEN Bit7 Bit6 Bit5 Bit7: TF2H: Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00 ...

Page 198

C8051F310/1/2/3/4/5/6/7 SFR Definition 17.9. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. SFR Definition ...

Page 199

Timer 3 Timer 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines the ...

Page 200

C8051F310/1/2/3/4/5/6/7 17.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 17.5. TMR3RLL holds the reload value for TMR3L; ...

Related keywords