C8051F314R Silicon Labs, C8051F314R Datasheet - Page 102

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C8051F314R

Manufacturer Part Number
C8051F314R
Description
8-bit Microcontrollers - MCU 8KB 10ADC
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F314R

Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
8 KB
Data Ram Size
1.25 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
LQFP-32
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
17
Data Rom Size
128 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
29
Number Of Timers
5
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
C8051F310/1/2/3/4/5/6/7
8.4.
Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter-
rupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped
(analog peripherals remain in their selected states; the external oscillator is not effected). Since clocks are
running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle. Stop mode consumes the least power. SFR Defini-
tion 8.12 describes the Power Control Register (PCON) used to control the CIP-51's power management
modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital
peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscil-
lators lowers power consumption considerably; however, a reset is required to restart the MCU.
8.4.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to
Section “9.6. PCA Watchdog
Timer Reset” on page 108
for more information on the use and configuration of the WDT.
Note: Any instruction that sets the IDLE bit should be immediately followed by an instruction that
has 2 or more opcode bytes. For example:
// in 'C':
PCON |= 0x01; // set IDLE bit
PCON
= PCON; // ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h ; set IDLE bit
MOV PCON, PCON; ... followed by a 3-cycle dummy instruction
If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during
the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from IDLE mode when
a future interrupt occurs.
102
Rev. 1.7

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