ST72T311J2T6 STMicroelectronics, ST72T311J2T6 Datasheet - Page 19

• Manufacturer Part Number: ST72T311J2T6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 8K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST72T311J2T6

• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 5.5 V
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 6
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 44
• Number Of Timers: 2
• On-chip Dac: No
• Program Memory Type: OTP EPROM
• Factory Pack Quantity: 160
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3 V

RESET (Cont’d)
3.2.4 Low Voltage Detector Reset
The on-chip Low Voltage Detector (LVD) gener-
ates a static reset when the supply voltage is be-
low a reference value. The LVD functions both
during power-on as well as when the power supply
drops (brown-out). The reference value for a volt-
age drop is lower than the reference value for pow-
er-on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
The LVD Reset circuitry generates a reset when
V
Provided the minimun V
the oscillator frequency) is above V
MCU can only be in two modes:
- under full software control or
- in static safe reset
In this condition, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
In noisy environments, the power supply may drop
for short periods and cause the Low Voltage De-
tector to generate a Reset too frequently. In such
Figure 16. Temporization timing diagram after an internal Reset
DD
V
V
LVDUP
LVDDOWN
is below:
when V
when V
V
Addresses
DD
DD
DD
is rising
is falling
DD
value (guaranteed for
V
LVDUP
LVDDOWN
Temporization (4096 CPU clock cycles)
, the
$FFFE
cases, it is recommended to use devices without
the LVD Reset option and to rely on the watchdog
function to detect application runaway conditions.
Figure 14. Low Voltage Detector Reset Function
Figure 15. Low Voltage Detector Reset Signal
Note: See electrical characteristics for values of
V
RESET
LVDUP
V
V
DD
DD
V
and V
LVDUP
DETECTOR RESET
LOW VOLTAGE
LVDDOWN
WATCHDOG
RESET
FROM
ST72E311 ST72T311
V
LVDDOWN
19
RESET
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