ST72T311J2T6 STMicroelectronics, ST72T311J2T6 Datasheet - Page 39

• Manufacturer Part Number: ST72T311J2T6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 8K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST72T311J2T6

• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 5.5 V
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 6
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 44
• Number Of Timers: 2
• On-chip Dac: No
• Program Memory Type: OTP EPROM
• Factory Pack Quantity: 160
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3 V

16-BIT TIMER (Cont’d)
5.3.3.3 Input Capture
In this section, the index, i , may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected by the
ICAP i pin (see figure 5).
The IC i R register is a read-only register.
The active transition is software programmable
through the IEDG i bit of Control Registers (CR i ).
Timing resolution is one count of the free running
counter: (
Procedure:
To use the input capture function, select the fol-
lowing in the CR2 register:
– Select the timer clock (CC[1:0]) (see
– Select the edge of the active transition on the
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as a floating input).
input capture coming from either the ICAP1 pin
or the ICAP2 pin
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as a floating input).
ICiR
f
CPU
/
CC[1:0]).
MS Byte
IC i HR
LS Byte
IC i LR
Table
1).
When an input capture occurs:
– The ICF i bit is set.
– The IC i R register contains the value of the free
– A timer interrupt is generated if the ICIE bit is set
Clearing the Input Capture interrupt request (i.e.
clearing the ICF i bit) is done in two steps:
1. Reading the SR register while the ICF i bit is set.
2. An access (read or write) to the IC i LR register.
Notes:
1. After reading the IC i HR register, the transfer of
2. The IC i R register contains the free running
3. The 2 input capture functions can be used
4. In One Pulse mode and PWM mode only the
5. The alternate inputs (ICAP1 & ICAP2) are
6. The TOF bit can be used with an interrupt in
running counter on the active transition on the
ICAP i pin (see
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
input capture data is inhibited and ICF i will
never be set until the IC i LR register is also
read.
counter value which corresponds to the most
recent input capture.
together even if the timer also uses the 2 output
compare functions.
input capture 2 function can be used.
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
Moreover if one of the ICAP i pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the IC i HR (see note
1).
order to measure events that exceed the timer
range (FFFFh).
Figure
6).
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