EVAL-ADXL344Z Analog Devices, EVAL-ADXL344Z Datasheet - Page 12

• Manufacturer Part Number: EVAL-ADXL344Z
• Description: Daughter Cards & OEM Boards EB
• Manufacturer: Analog Devices
• Series: ADXL344r

Specifications of EVAL-ADXL344Z

• Rohs: yes
• Product: Breakout Boards
• Description/function: 3 axis accelerometer evaluation board
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.7 V to 2.75 V
• Factory Pack Quantity: 1
• For Use With: ADXL344

ADXL344
SERIAL COMMUNICATIONS
I
the
is tied high to V
V
default mode if the CS pin is left unconnected. Therefore, not
taking these precautions may result in an inability to communicate
with the part. In SPI mode, the CS pin is controlled by the bus
master. In both SPI and I
from the
writes to the ADXL344.
SPI
For SPI, either 3- or 4-wire configuration is possible, as shown in
the connection diagrams in Figure 22 and Figure 23. Clearing the
SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31)
selects 4-wire mode, whereas setting the SPI bit selects 3-wire
mode. The maximum SPI clock speed is 5 MHz with 100 pF
maximum loading, and the timing scheme follows clock polarity
(CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to
the
processor are configured, the CS pin should be brought high
before changing the clock polarity and phase. When using 3-wire
SPI, it is recommended that the SDO pin be either pulled up to
V
CS is the serial port enable line and is controlled by the SPI
master. This line must go low at the start of a transmission and
high at the end of a transmission, as shown in Figure 25. SCLK
is the serial port clock and is supplied by the SPI master. SCLK
should idle high during a period of no transmission. SDI and
SDO are the serial data input and output, respectively. Data is
updated on the falling edge of SCLK and should be sampled on
the rising edge of SCLK.
To read or write multiple bytes in a single transmission, the
multiple-byte bit, located after the R/ W bit in the first byte transfer
2
C and SPI digital communications are available. In both cases,
DD I/O
DD I/O
ADXL344
ADXL344
or be driven by an external controller because there is no
or pulled down to GND via a 10 kΩ resistor.
ADXL344
operates as a slave. I
before the clock polarity and phase of the host
Figure 22. 3-Wire SPI Connection Diagram
Figure 23. 4-Wire SPI Connection Diagram
ADXL344
ADXL344
DD I/O
to the master device should be ignored during
. The CS pin should always be tied high to
SCLK
SCLK
SDIO
SDO
SDO
SDI
CS
CS
2
C modes of operation, data transmitted
2
C mode is enabled if the CS pin
PROCESSOR
PROCESSOR
CS
MOSI
MISO
SCLK
CS
MOSI
MISO
SCLK
Rev. 0 | Page 12 of 40
(MB in Figure 25 to Figure 27), must be set. After the register
addressing and the first byte of data, each subsequent set of
clock pulses (eight clock pulses) causes the
to the next register for a read or write. This shifting continues
until the clock pulses cease and CS is deasserted. To perform reads
or writes on different, nonsequential registers, CS must be
deasserted between transmissions and the new register must be
addressed separately.
The timing diagram for 3-wire SPI reads or writes is shown in
Figure 27. The 4-wire equivalents for SPI writes and reads are
shown in Figure 25 and Figure 26, respectively. For correct
operation of the part, the logic thresholds and timing parameters
in Table 9 and Table 10 must be met at all times.
Use of the 3200 Hz and 1600 Hz output data rates is only
recommended with SPI communication rates greater than or
equal to 2 MHz. The 800 Hz output data rate is recommended
only for communication speeds greater than or equal to 400 kHz,
and the remaining data rates scale proportionally. For example,
the minimum recommended communication speed for a 200 Hz
output data rate is 100 kHz. Operation at an output data rate
above the recommended maximum may result in undesirable
effects on the acceleration data, including missing samples or
additional noise.
Preventing Bus Traffic Errors
The
transactions and for enabling I
is used on a SPI bus with multiple devices, its CS pin is held
high while the master communicates with the other devices.
There may be conditions where a SPI command transmitted to
another device looks like a valid I
ADXL344
mode, and may interfere with other bus traffic. Unless bus
traffic can be adequately controlled to assure such a condition
never occurs, it is recommended to add a logic gate in front of
the SDI pin as shown in Figure 24. This OR gate holds the SDI
line high when CS is high to prevent SPI bus traffic at the
ADXL344
this recommendation applies only in cases where the
is used on a SPI bus with multiple devices.
Figure 24. Recommended SPI Connection Diagram when Using Multiple SPI
ADXL344
interprets this as an attempt to communicate in I
from appearing as an I
ADXL344
CS pin is used both for initiating SPI
SCLK
SDO
SDI
CS
Devices on a Single Bus
2
C mode. When the
2
2
C start command. Note that
C command. In this case, the
PROCESSOR
MOSI
MISO
SCLK
CS
ADXL344
Data Sheet
ADXL344
ADXL344
to point
2
C