EVAL-ADXL344Z Analog Devices, EVAL-ADXL344Z Datasheet - Page 27

• Manufacturer Part Number: EVAL-ADXL344Z
• Description: Daughter Cards & OEM Boards EB
• Manufacturer: Analog Devices
• Series: ADXL344r

Specifications of EVAL-ADXL344Z

• Rohs: yes
• Product: Breakout Boards
• Description/function: 3 axis accelerometer evaluation board
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.7 V to 2.75 V
• Factory Pack Quantity: 1
• For Use With: ADXL344

Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY DECOUPLING
A 1 μF tantalum capacitor (C
(C
recommended to adequately decouple the accelerometer from
noise on the power supply. If additional decoupling is necessary,
a resistor or ferrite bead, no larger than 100 Ω, in series with V
may be helpful. Additionally, increasing the bypass capacitance
on V
ceramic capacitor may also improve noise.
Care should be taken to ensure that the connection from the
ADXL344
because noise transmitted through ground has an effect similar
to noise transmitted through V
V
the V
supplies as previously mentioned may be necessary.
MECHANICAL CONSIDERATIONS FOR MOUNTING
The
close to a hard mounting point of the PCB to the case. Mounting
the
Figure 33, may result in large, apparent measurement errors due
to undampened PCB vibration. Locating the accelerometer near
a hard mounting point ensures that any PCB vibration at the
accelerometer is above the accelerometer’s mechanical sensor
resonant frequency and, therefore, effectively invisible to the
accelerometer. Multiple mounting points close to the sensor
and/or a thicker PCB also help to reduce the effect of system
resonance on the performance of the sensor.
DD I/O
INTERRUPT
I/O
CONTROL
ADXL344
) at V
ADXL344
S
S
to a 10 μF tantalum capacitor in parallel with a 0.1 μF
supply. If this is not possible, additional filtering of the
be separate supplies to minimize digital clock noise on
DD I/O
ground to the power supply ground has low impedance
Figure 33. Incorrectly Placed Accelerometers
at an unsupported PCB location, as shown in
placed close to the
should be mounted on the PCB in a location
MOUNTING POINTS
C
S
Figure 32. Applications Diagram
ACCELEROMETERS
INT1
INT2
V
V
S
S
SDO/ALT ADDRESS
ADXL344
PCB
S
GND
) at V
SDA/SDI/SDIO
S
SCL/SCLK
. It is recommended that V
V
V
DD I/O
S
DD I/O
ADXL344
and a 0.1 μF ceramic capacitor
CS
C
I/O
supply pins is
3-WIRE OR
4-WIRE SPI
OR I
INTERFACE
2
C
S
and
Rev. 0 | Page 27 of 40
S
TAP DETECTION
The tap interrupt function is capable of detecting either single
or double taps. The following parameters are shown in Figure 34
for a valid single-tap event and a valid double-tap event:
•
•
•
•
If only the single-tap function is in use, the single-tap interrupt
is triggered when the acceleration goes below the threshold, as
long as DUR has not been exceeded. If both single and double-
tap functions are in use, the single-tap interrupt is triggered
when the double-tap event has been either validated or
invalidated.
Several events can occur to invalidate the second tap of a
double-tap event. First, if the suppress bit in the TAP_AXES
register (Address 0x2A) is set, any acceleration spike above the
threshold during the latency time (set by the latent register)
invalidates the double-tap detection, as shown in Figure 35.
Figure 34. Tap Interrupt Function with Valid Single and Double Taps
The tap detection threshold is defined by the THRESH_TAP
register (Address 0x1D).
The maximum tap duration time is defined by the DUR
register (Address 0x21).
The tap latency time is defined by the latent register
(Address 0x22) and is the waiting period from the end of
the first tap until the start of the time window when a
second tap can be detected, which is determined by the
value in the window register (Address 0x23).
The interval after the latency time (set by the latent register) is
defined by the window register. Although a second tap must
begin after the latency time has expired, it need not finish
before the end of the time defined by the window register.
LATENCY
(LATENT)
TIME
FIRST TAP
TIME LIMIT FOR
SINGLE-TAP
INTERRUPT
TAPS (DUR)
SECOND TAP (WINDOW)
TIME WINDOW FOR
SECOND TAP
DOUBLE-TAP
INTERRUPT
THRESHOLD
(THRESH_TAP)
ADXL344