EVAL-ADXL344Z Analog Devices, EVAL-ADXL344Z Datasheet - Page 32

• Manufacturer Part Number: EVAL-ADXL344Z
• Description: Daughter Cards & OEM Boards EB
• Manufacturer: Analog Devices
• Series: ADXL344r

Specifications of EVAL-ADXL344Z

• Rohs: yes
• Product: Breakout Boards
• Description/function: 3 axis accelerometer evaluation board
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.7 V to 2.75 V
• Factory Pack Quantity: 1
• For Use With: ADXL344

ADXL344
By setting the INT_ORIENT bit (Bit D7) of the ORIENT_CONF
register (Address 0x3B), an interrupt can be generated when the
device is placed into a new valid orientation. Only one mode of
orientation detection, 2D or 3D, can generate an interrupt at a
time. The orientation detection mode is selected by setting or
clearing the INT_3D bit (Bit D3) of the ORIENT_CONF register
(Address 0x3B). For more details, refer to the Register 0x3B—
ORIENT_CONF (Read/Write) section.
Writing to the BW_RATE register or placing the part into standby
mode resets the orientation feature, clearing the orientation filter
and the orientation status. These actions cause an orientation
interrupt (if enabled), however, if the orientation during the
next output sample is different from the default value (+X for
2D orientation detection and undefined for 3D orientation).
DATA FORMATTING OF UPPER DATA RATES
Formatting of output data at the 3200 Hz and 1600 Hz output
data rates changes depending on the mode of operation (full-
resolution or fixed 10-bit) and the selected output range.
THE ±4g AND ±8g FULL-RESOLUTION MODES HAVE THE SAME LSB LOCATION AS THE ±2g
AND ±16g FULL-RESOLUTION MODES, BUT THE MSB LOCATION CHANGES TO BIT D2 AND
BIT D3 OF THE DATAx1 REGISTER FOR ±4g AND ±8g, RESPECTIVELY.
DATAx1 REGISTER
OUTPUT DATA-WORD FOR
±16g, FULL-RESOLUTION MODE.
FOR 3200Hz AND 1600Hz OUTPUT DATA RATES, THE LSB IN THESE MODES IS ALWAYS 0.
ADDITIONALLY, ANY BITS TO THE RIGHT OF THE LSB ARE ALWAYS 0 WHEN THE OUTPUT
DATA IS LEFT JUSTIFIED.
DATAx1 REGISTER
MSB FOR ALL MODES
OF OPERATION WHEN
LEFT JUSTIFIED.
D7
D7
D7
D7
D6
D6
D6
D6
D5
D5
D5
D5
D4
D4
Figure 40. Data Formatting When Output Data Is Right Justified
D4
D4
Figure 41. Data Formatting When Output Data Is Left Justified
LSB FOR ±2g, FULL-RESOLUTION
LSB FOR ±16g, FULL-RESOLUTION MODE.
D3
LSB FOR ±4g, FULL-RESOLUTION MODE.
LSB FOR ±8g, FULL-RESOLUTION MODE.
D3
D3
D3
D2
D2
D2
D2
AND ALL 10-BIT MODES.
D1
D1
D1
D1
Rev. 0 | Page 32 of 40
D0
D0
D0
D0
D7
D7
D7
D7
When using the 3200 Hz or 1600 Hz output data rates in
full-resolution or ±2 g, 10-bit operation, the LSB of the output
data-word is always 0. When data is right justified, this corresponds
to Bit D0 of the DATAx0 register, as shown in Figure 40. When
data is left justified and the part is operating in ±2 g, 10-bit mode,
the LSB of the output data-word is Bit D6 of the DATAx0 register.
In full-resolution operation when data is left justified, the location
of the LSB changes according to the selected output range. For a
range of ±2 g, the LSB is Bit D6 of the DATAx0 register; for ±4 g,
Bit D5 of the DATAx0 register; for ±8 g, Bit D4 of the DATAx0
register; and for ±16 g, Bit D3 of the DATAx0 register. This is
shown in Figure 41.
The use of 3200 Hz and 1600 Hz output data rates for fixed 10-bit
operation in the ±4 g, ±8 g, and ±16 g output ranges provides an
LSB that is valid and that changes according to the applied accel-
eration. Therefore, in these modes of operation, Bit D0 is not
always 0 when output data is right justified, and Bit D6 is not
always 0 when output data is left justified. Operation at any data
rate of 800 Hz or lower also provides a valid LSB in all ranges and
modes that change according to the applied acceleration.
D6
D6
FULL-RESOLUTION AND ALL 10-BIT MODES.
D6
D6
OUTPUT DATA-WORD FOR THE ±2g,
D5
D5
D5
D5
D4
D4
D4
D4
D3
D3
D3
D3
DATAx0 REGISTER
DATAx0 REGISTER
D2
D2
D2
D2
D1
D1
D1
D1
D0
0
D0
0
Data Sheet