MA330026 Microchip Technology, MA330026 Datasheet - Page 171

• Manufacturer Part Number: MA330026
• Description: Daughter Cards & OEM Boards dsPIC33FJ16MC102 Plug-In Module
• Manufacturer: Microchip Technology

Specifications of MA330026

• Rohs: yes
• Product: Plug-In Modules
• Core: PIC
• Data Bus Width: 16 bit
• Description/function: dsPIC33F MC 28 Pin QFN to 100 Pin Plug-in-Module
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• For Use With: DM330021, DM330022, DM330023

REGISTER 16-2:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
Note 1:
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
SSEN
R/W-0
U-0
—
2:
3:
(2)
The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
This bit must be cleared when FRMEN = 1.
Do not set both Primary and Secondary prescalers to a value of 1:1.
Unimplemented: Read as ‘0’
DISSCK: Disable SCKx pin bit (SPI Master modes only)
1 = Internal SPI clock is disabled, pin functions as I/O
0 = Internal SPI clock is enabled
DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by module; pin functions as I/O
0 = SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
CKE: SPIx Clock Edge Select bit
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
SSEN: Slave Select Enable bit
1 = SSx pin used for Slave mode
0 = SSx pin not used by module. Pin controlled by port function
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
R/W-0
CKP
U-0
—
SPI
X
CON1: SPIx CONTROL REGISTER 1
‘1’ = Bit is set
W = Writable bit
MSTEN
R/W-0
U-0
—
(2)
DISSCK
R/W-0
R/W-0
(1)
(Slave mode)
Preliminary
SPRE<2:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DISSDO
R/W-0
R/W-0
(3)
MODE16
R/W-0
R/W-0
x = Bit is unknown
R/W-0
R/W-0
SMP
PPRE<1:0>
DS70652C-page 171
CKE
R/W-0
R/W-0
(3)
(1)
bit 8
bit 0