MA330026 Microchip Technology, MA330026 Datasheet - Page 72
MA330026
Manufacturer Part Number
MA330026
Description
Daughter Cards & OEM Boards dsPIC33FJ16MC102 Plug-In Module
Manufacturer
Microchip Technology
Datasheet
1.MA330026.pdf
(322 pages)
Specifications of MA330026
Rohs
yes
Product
Plug-In Modules
Core
PIC
Data Bus Width
16 bit
Description/function
dsPIC33F MC 28 Pin QFN to 100 Pin Plug-in-Module
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
For Use With
DM330021, DM330022, DM330023
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MA330026
Manufacturer:
MICROCHIP
Quantity:
12 000
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dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
6.1
The dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/
102 family of devices have two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a POR or a BOR. On a cold
Reset, the FNOSC configuration bits in the FOSC
device configuration register selects the device clock
source.
TABLE 6-1:
DS70652C-page 72
Note 1:
FRC, FRCDIV16,
Oscillator Mode
FRCDIVN
FRCPLL
MSPLL
ECPLL
2:
3:
SOSC
LPRC
MS
System Reset
HS
EC
T
times vary with crystal characteristics, load capacitance, etc.
T
10 MHz crystal and T
T
OSCD
OST
LOCK
= Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, T
OSCILLATOR DELAY
= PLL lock time (1.5 ms nominal), if PLL is enabled.
= Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up
Startup Delay
Oscillator
T
T
T
T
T
T
T
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
—
—
OST
= 32 ms for a 32 kHz crystal.
Oscillator Startup
Preliminary
Timer
T
T
T
T
OST
OST
OST
OST
—
—
—
—
—
A warm Reset is the result of all other Reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
(COSC<2:0>)
(OSCCON<14:12>) register.
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is shown in
PLL Lock Time
T
T
T
LOCK
LOCK
LOCK
bits
—
—
—
—
—
—
in
© 2011 Microchip Technology Inc.
the
Figure
T
OSCD
OST
Oscillator
T
T
T
T
OSCD
Total Delay
= 102.4 μs for a
OSCD
OSCD
OSCD
6-2.
+ T
T
T
T
OSCD
OSCD
LOCK
OST
—
+ T
+ T
+ T
+ T
LOCK
+ T
OST
OST
OST
Control
LOCK
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