MA330026 Microchip Technology, MA330026 Datasheet - Page 178

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MA330026

Manufacturer Part Number
MA330026
Description
Daughter Cards & OEM Boards dsPIC33FJ16MC102 Plug-In Module
Manufacturer
Microchip Technology
Datasheet

Specifications of MA330026

Rohs
yes
Product
Plug-In Modules
Core
PIC
Data Bus Width
16 bit
Description/function
dsPIC33F MC 28 Pin QFN to 100 Pin Plug-in-Module
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
For Use With
DM330021, DM330022, DM330023

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MA330026
Manufacturer:
MICROCHIP
Quantity:
12 000
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
REGISTER 17-1:
DS70652C-page 178
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ACKDT: Acknowledge Data bit (when operating as I
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(when operating as I
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
0 = Acknowledge sequence not in progress
RCEN: Receive Enable bit (when operating as I
1 = Enables Receive mode for I
0 = Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence
0 = Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
0 = Repeated Start condition not in progress
SEN: Start Condition Enable bit (when operating as I
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence
0 = Start condition not in progress
Hardware clear at end of master Acknowledge sequence
master Repeated Start sequence
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
2
C master, applicable during master receive)
2
C. Hardware clear at end of eighth bit of master receive data byte
Preliminary
2
C master)
2
2
2
C master, applicable during master receive)
C master)
C master)
2
C master)
© 2011 Microchip Technology Inc.

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