AT28LV010-20TU Atmel, AT28LV010-20TU Datasheet - Page 4

• Manufacturer Part Number: AT28LV010-20TU
• Description: IC EEPROM 1MBIT 200NS 32TSOP
• Manufacturer: Atmel

Specifications of AT28LV010-20TU

• Format - Memory: EEPROMs - Parallel
• Memory Type: EEPROM
• Memory Size: 1M (128K x 8)
• Speed: 200ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TSOP
• Capacitance, Input: 4 pF
• Capacitance, Output: 8 pF
• Current, Input, Leakage: 1 μA
• Current, Operating: 15 mA
• Current, Output, Leakage: 1
• Data Retention: 10 yrs.
• Density: 1M
• Organization: 128K×8
• Package Type: TSOP
• Power Dissipation: 54 mW
• Temperature, Operating: -40 to +85 °C
• Time, Access: 200 ns
• Time, Address Hold: 100
• Voltage, Input, High: 2 V
• Voltage, Input, Low: 0.8 V
• Voltage, Output, High: 2.4 V
• Voltage, Output, Low: 0.45 V
• Voltage, Supply: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3
4.4
4.5
4.5.1
4.5.2
4
DATA Polling
Toggle Bit
Data Protection
AT28LV010
Hardware Protection
Software Data Protection
The AT28LV010 features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is
valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime
during the write cycle.
In addition to DATA Polling the AT28LV010 provides another method for determining the end
of a write cycle. During the write operation, successive attempts to read data from the device
will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop
toggling and valid data will be read. Reading the toggle bit may begin at any time during the
write cycle.
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel
the memory against inadvertent writes.
Hardware features protect against inadvertent writes to the AT28LV010 in the following ways:
(a) V
time out 5 ms (typical) before allowing a write; (b) write inhibit – holding any one of OE low, CE
high or WE high inhibits write cycles; and (c) noise filter – pulses of less than 15 ns (typical) on
the WE or CE inputs will not initiate a write cycle.
The AT28LV010 incorporates the industry standard software data protection (SDP) function.
Unlike standard 5-volt only EEPROM’s, the AT28LV010 has SDP enabled at all times. There-
fore, all write operations must be preceded by the SDP command sequence.
The data in the 3-byte command sequence is not written to the device; the addresses in the
command sequence can be utilized just like any other location in the device. Any attempt to
write to the device without the 3-byte sequence will start the internal timers. No data will be
written to the device. However, for the duration of t
ing operations.
CC
power-on delay – once V
®
has incorporated both hardware and software features that will protect
CC
has reached 2.0V (typical) the device will automatically
WC
, read operations will effectively be poll-
0395F–PEEPR–08/09