DK-START-5AGXB3NES Altera Corporation, DK-START-5AGXB3NES Datasheet - Page 39

• Manufacturer Part Number: DK-START-5AGXB3NES
• Description: Programmable Logic IC Development Tools FPGA Starter Kit For 5AGXFB3H4F
• Manufacturer: Altera Corporation
• Type: FPGAr

Specifications of DK-START-5AGXB3NES

• Rohs: yes
• Product: Starter Kits
• Tool Is For Evaluation Of: 5AGXB3
• For Use With: 5AGXB3

Chapter 6: Board Test System
The Power Monitor
The Power Monitor
February 2013 Altera Corporation
1
Status
These controls display current transaction performance analysis information collected
since you last clicked Start:
■
■
■
■
The Power Monitor measures and reports current power information. To start the
application, click Power Monitor in the Board Test System application.
You can also run the Power Monitor as a stand-alone application. PowerMonitor.exe
resides in the <install
dir>\kits\arriaVGX_5agxfb3hf35_start\examples\board_test_system directory. On
Windows, click Start > All Programs > Altera > Arria V GX Starter Kit <version> >
Power Monitor to start the application.
The Power Monitor communicates with the MAX V device on the board through the
JTAG bus. A power monitor circuit attached to the MAX V device allows you to
measure the power that the Arria V GX FPGA device is consuming.
TX and RX performance bars—Show the percentage of maximum theoretical data
rate that the requested transactions are able to achieve.
PLL lock—Shows the PLL locked or unlocked state.
Pattern sync—Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected after channel
lock is acquired.
Channel lock—Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded, and all TX and RX PLL lanes are
phase locked to data; RX lanes are word aligned and deskewed.
Arria V GX Starter Kit
User Guide
6–17