IS61LV12816L-10TLI ISSI, Integrated Silicon Solution Inc, IS61LV12816L-10TLI Datasheet - Page 11

• Manufacturer Part Number: IS61LV12816L-10TLI
• Description: IC SRAM 2MBIT 10NS 44TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LV12816L-10TLI

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 2M (128K x 16)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSOP II
• Density: 2Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 65mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS61LV12816L
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. F
10/27/05
WRITE CYCLE NO. 4
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t
referenced to the rising or falling edge of the signal that terminates the Write.
ADDRESS
UB, LB
D
OUT
WE
D
OE
CE
IN
LOW
DATA UNDEFINED
(LB, UB Controlled, Back-to-Back Write)
t
HZWE
ADDRESS 1
t
SD
t
t
WORD 1
SA
WC
t
PBW
HIGH-Z
DATA
VALID
IN
1-800-379-4774
t
t
HD
HA
t
SA
ADDRESS 2
t
t
(1,3)
SD
WC
WORD 2
t
PBW
DATA
VALID
IN
t
LZWE
SA
t
HD
t
, t
HA
HA
, t
SD
, and t
UB_CEWR4.eps
HD
ISSI
timing is
11
®