IS61NLP12836B-200TQLI-TR ISSI, Integrated Silicon Solution Inc, IS61NLP12836B-200TQLI-TR Datasheet

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IS61NLP12836B-200TQLI-TR

Manufacturer Part Number
IS61NLP12836B-200TQLI-TR
Description
IC SRAM 4MBIT 200MHZ 100TQFP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS61NLP12836B-200TQLI-TR

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
4M (128K x 36)
Speed
200MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS61NLP12836B-200TQLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS61NLP12836B/IS61NVP12836B
IS61NLP25618A/IS61NVP25618A
128K x 32, 128K x 36, and 256K x 18
4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
• Interleaved or linear burst sequence control us-
• Three chip enables for simple depth expansion
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and 119-
• Power supply:
• Industrial temperature available
• Lead-free available
FAST ACCESS TIME
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
09/10/07
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
data and control
ing MODE input
and address pipelining
ball PBGA packages
NVP: V
NLP: V
Symbol
t
t
kq
kc
dd
dd
3.3V (± 5%), V
2.5V (± 5%), V
Parameter
Clock Access Time
Cycle Time
Frequency
ddq
ddq
3.3V/2.5V (± 5%)
2.5V (± 5%)
-250
250
2.6
4
DESCRIPTION
The 4 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 128K words by 32 bits, 128K words by 36
bits, and 256K words by 18 bits, fabricated with
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
device will hold their previous values.
All Read,Write and Deselect cycles are initiated by the ADV
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock inputs and when WE is
LOW. Separate byte enables allow individual bytes to be
written.
sequence.When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
A burst mode pin (MODE) defines the order of the burst
-200
200
3.1
5
Units
MHz
ns
ns
SEPTEMBER 2007
ISSI
's
1

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IS61NLP12836B-200TQLI-TR Summary of contents

Page 1

... IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • ...

Page 2

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A BLOCK DIAGRAM x 32/x 36: A [0:16] or ADDRESS x 18: A [0:17] REGISTER CLK CONTROL LOGIC K CKE CE CE2 CE2 CONTROL } ADV REGISTER WE BWŸ X (X=a,b,c DQx/DQPx 2 A2-A16 or A2-A17 MODE BURST ADDRESS A0-A1 A'0-A'1 COUNTER WRITE WRITE ADDRESS ADDRESS REGISTER REGISTER CONTROL ...

Page 3

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A Bottom View 119-Ball BGA 1 mm Ball Pitch Ball Array Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 Bottom View 165-Ball 15mm BGA 1 mm Ball Pitch Ball Array 3 ...

Page 4

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A PIN CONFIgURATION — 128K CE2 C DQPc NC V ddq D DQc DQc V ddq E DQc DQc V ddq F DQc DQc V ddq G DQc DQc V ddq DQd DQd V ddq K DQd DQd V ddq L DQd DQd V ddq M DQd DQd V ddq N DQPd NC V ddq MODE NC A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired ...

Page 5

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 119-PIN PBgA PACKAgE CONFIGURATION DDQ B NC CE2 NC C DQc DQPc D DQc DQc E V DQc F DDQ DQc DQc G H DQc DQc DDQ K DQd DQd L DQd DQd V DQd M DDQ DQd DQd N DQd DQPd DDQ Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. ...

Page 6

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 165-PIN PBgA PACKAgE CONFIGURATION CE2 DDQ DQb DDQ V DQb E NC DDQ DQb DDQ V DDQ G NC DQb DDQ DQb DQb DDQ DQb DDQ V M DQb NC DDQ NC N DQPb V DDQ MODE Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. ...

Page 7

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 119-PIN PBgA PACKAgE CONFIGURATION DDQ B NC CE2 DQb D E DQb DDQ NC DQb G H DQb DDQ K DQb NC L DQb DQb DDQ DQb DQPb DDQ Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. ...

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... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A PIN CONFIGURATION 100-Pin TQFP 100 DQPc 2 DQc 3 DQc 4 V DDQ 5 Vss 6 DQc 7 DQc 8 DQc 9 DQc 10 Vss 11 V DDQ 12 DQc 13 DQc Vss 18 DQd 19 DQd 20 V DDQ 21 Vss 22 DQd 23 DQd 24 DQd 25 DQd 26 Vss 27 V DDQ 28 DQd DQd 29 DQPd 128K x 36 ...

Page 9

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A PIN CONFIGURATION 100-Pin TQFP 100 DDQ 5 Vss DQb 9 DQb 10 Vss 11 V DDQ 12 DQb 13 DQb Vss 17 18 DQb 19 DQb 20 V DDQ 21 Vss DQb 22 23 DQb 24 DQPb Vss 27 V DDQ 256K x 18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus ...

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... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A STATE DIAGRAM BEGIN READ READ READ BURST BURST BURST READ SYNCHRONOUS TRUTH TABLE Address Operation Used Not Selected N/A Not Selected N/A Not Selected N/A Not Selected Continue N/A Begin Burst Read External Address Continue Burst Read Next Address ...

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... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ASYNCHRONOUS TRUTH TABLE Operation ZZ Sleep Mode H Read L L Write L Deselected L Notes means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. ...

Page 12

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A WRITE TRUTH TABLE (x32/x36) Operation WE READ H WRITE BYTE a L WRITE BYTE b L WRITE BYTE c L WRITE BYTE d L WRITE ALL BYTEs L WRITE ABORT/NOP L Notes : 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. ...

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... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A LINEAR BURST ADDRESS TABLE A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINgS Symbol Parameter T Storage Temperature STG P Power Dissipation d I Output Current (per I/O) ouT Voltage Relative ouT V Voltage Relative for Address and Control Inputs Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

Page 14

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions V Output HIGH Voltage Output LOW Voltage Input HIGH Voltage ( Input LOW Voltage ( Input Leakage Current Output Leakage Current V lo Note: 1. Overshoot: V (AC) < 2.0V (Pulse width less than POWER SUPPLY CHARACTERISTICS Symbol Parameter ...

Page 15

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A CAPACITANCE (1,2) Symbol Parameter c Input Capacitance In c Input/Output Capacitance ouT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...

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... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT Z = 50Ω O OUTPUT Figure 3 16 Unit 0V to 2.5V 1 ...

Page 17

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A READ/WRITE CYCLE SWITCHINg CHARACTERISTICS Symbol Parameter fmax Clock Frequency t Cycle Time kc t Clock High Time kh t Clock Low Time kl t Clock Access Time kq t Clock High to Output Invalid (2) kqx t Clock High to Output Low-Z (2,3) kqlZ t Clock High to Output High-Z ...

Page 18

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Parameter I Current during SLEEP MODE active to input ignored PdS t ZZ inactive to input sampled PuS t ZZ active to SLEEP current ZZI t ZZ inactive to exit SLEEP current rZZI SLEEP MODE TIMINg CLK t PDS ZZ setup cycle ZZ t ZZI ...

Page 19

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A READ CYCLE TIMINg CLK t t ADVS ADVH ADV Address WRITE CKE t t CES CEH OEQ t OEHZ Data Out Q1-1 NOTES: WRITE = L means and BWx = and BWX = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — ...

Page 20

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A WRITE CYCLE TIMINg t KH CLK t KC ADV Address A1 A2 WRITE CKE CE OE Data In D1-1 t OEHZ Data Out Q0-3 Q0-4 NOTES: WRITE = L means and BWx = and BWX = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L ...

Page 21

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A SINgLE READ/WRITE CYCLE TIMINg CLK CKE Address WRITE CE ADV OE t OEQ t OELZ Data Out Q1 Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com Rev ...

Page 22

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A CKE OPERATION TIMINg CLK CKE Address A1 A2 WRITE CE ADV OE Data Out Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = KQHZ t KQLZ Q1 Integrated Silicon Solution, Inc. — www.issi.com ...

Page 23

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A CE OPERATION TIMINg CLK CKE A1 A2 Address WRITE CE ADV OE t OEQ t OELZ Q1 Data Out Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com Rev ...

Page 24

... DD DDq Order Part Number 128Kx32 IS61NLP12832B-250TQ IS61NLP12832B-250B3 IS61NLP12832B-250B2 IS61NLP12832B-200TQ IS61NLP12832B-200B3 IS61NLP12832B-200B2 128Kx36 IS61NLP12836B-250TQ IS61NLP12836B-250B3 IS61NLP12836B-250B2 IS61NLP12836B-200TQ IS61NLP12836B-200B3 IS61NLP12836B-200B2 256Kx18 IS61NLP25618A-250TQ IS61NLP25618A-250B3 IS61NLP25618A-250B2 IS61NLP25618A-200TQ IS61NLP25618A-200B3 IS61NLP25618A-200B2 Integrated Silicon Solution, Inc. — www.issi.com Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA ...

Page 25

... DD DDq Order Part Number 128Kx32 IS61NLP12832B-250TQI IS61NLP12832B-250B3I IS61NLP12832B-250B2I IS61NLP12832B-200TQI IS61NLP12832B-200TQLI IS61NLP12832B-200B3I IS61NLP12832B-200B2I 128Kx36 IS61NLP12836B-250TQI IS61NLP12836B-250B3I IS61NLP12836B-250B2I IS61NLP12836B-200TQI IS61NLP12836B-200TQLI IS61NLP12836B-200B3I IS61NLP12836B-200B2I IS61NLP12836B-200B2LI 256Kx18 IS61NLP25618A-250TQI IS61NLP25618A-250B3I IS61NLP25618A-250B2I IS61NLP25618A-200TQI IS61NLP25618A-200TQLI IS61NLP25618A-200B3I IS61NLP25618A-200B3LI IS61NLP25618A-200B2I Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free ...

Page 26

... IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ORDERINg INFORMATION (V Commercial Range: 0°C to +70°C Access Time 250 200 250 200 Industrial Range: -40°C to +85°C Access Time 250 200 250 200 26 = 2.5V/V = 2.5V) DD DDq Order Part Number 128Kx36 IS61NVP12836B-250TQ IS61NVP12836B-250B3 IS61NVP12836B-250B2 IS61NVP12836B-200TQ IS61NVP12836B-200B3 IS61NVP12836B-200B2 256Kx18 ...

Page 27

PACKAGING INFORMATION Plastic Ball Grid Array Package Code: B (119-pin MILLIMETERS Sym. Min. Max. N0. Leads 119 A — 2.41 A1 0.50 0.70 A2 0.80 1.00 A3 1.30 1.70 A4 0.56 BSC b 0.60 0.90 D 21.80 ...

Page 28

PACKAGING INFORMATION Ball Grid Array Package Code: B (165-pin) TOP VIEW A1 CORNER BGA - 13mm ...

Page 29

PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code Thin Quad Flat Pack (TQ) Millimeters Inches Symbol Min Max Min Ref. Std. No. Leads (N) 100 A — 1.60 — A1 0.05 0.15 ...

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