MT48V8M16LFB4-8 IT:G Micron Technology Inc, MT48V8M16LFB4-8 IT:G Datasheet - Page 40
![IC SDRAM 128MBIT 125MHZ 54VFBGA](/photos/7/22/72286/557-54-fbga_sml.jpg)
MT48V8M16LFB4-8 IT:G
Manufacturer Part Number
MT48V8M16LFB4-8 IT:G
Description
IC SDRAM 128MBIT 125MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Specifications of MT48V8M16LFB4-8 IT:G
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (8Mx16)
Speed
125MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-VFBGA
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
19/8/7ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
2.5V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
100mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Burst Read/Single Write
Figure 30:
CONCURRENT Auto Precharge
READ with Auto Precharge
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN
Clock Suspend During READ Burst
Notes:
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of 1), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
COMMAND
1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
An access command (READ or WRITE) to another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
INTERNAL
ADDRESS
rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (Figure 31 on page 41).
interrupt a READ on bank n when registered. DQM should be used 2 clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 32 on page 41).
CLOCK
CLK
CKE
DQ
T0
BANK,
COL n
READ
T1
NOP
T2
NOP
40
D
OUT
n
TRANSITIONING DATA
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n + 1
D
OUT
T4
NOP
128Mb: x16, x32 Mobile SDRAM
T5
NOP
n + 2
D
OUT
DON’T CARE
T6
NOP
D
n + 3
OUT
©2001 Micron Technology, Inc. All rights reserved.
READs