MT46V128M4BN-5B:F Micron Technology Inc, MT46V128M4BN-5B:F Datasheet - Page 69
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MT46V128M4BN-5B:F
Manufacturer Part Number
MT46V128M4BN-5B:F
Description
IC DDR SDRAM 512MBIT 5NS 60FBGA
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V32M16P-5BF_TR.pdf
(91 pages)
Specifications of MT46V128M4BN-5B:F
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
512M (128Mx4)
Speed
5ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
60-FBGA
Organization
128Mx4
Density
512Mb
Address Bus
15b
Access Time (max)
700ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.6V
Package Type
FBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.5V
Supply Current
195mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT46V128M4BN-5B:F
Manufacturer:
MICRON
Quantity:
1 218
Company:
Part Number:
MT46V128M4BN-5B:F
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT46V128M4BN-5B:F
Manufacturer:
MICRON/镁光
Quantity:
20 000
Company:
Part Number:
MT46V128M4BN-5B:F TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 34:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Command
BA0, BA1
Case 1:
Case 2:
Address
DQS
DQS
CK#
CKE
A10
DM
DQ
DQ
CK
t
t
AC (MIN) and
AC (MAX) and
Bank READ – Without Auto Precharge
t
t
IS
NOP
IS
T0
t
1
Notes:
t
IH
t
IH
DQSCK (MIN)
t
DQSCK (MAX)
t
t
Bank x
IS
IS
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. The PRECHARGE command can only be applied at T5 if
4. Disable auto precharge.
5. “Don’t Care” if A10 is HIGH at T5.
6. DO n (or b) = data-out from column n (or column b); subsequent elements are provided in
7. Refer to Figure 35 on page 70, Figure 36 on page 71, and Figure 37 on page 72 for detailed
Row
Row
ACT
T1
t
t
times.
the programmed order.
DQS and DQ timing.
IH
IH
t
CK
t
t RAS 3
t
RCD
RC
NOP
T2
1
t
CH
t
CL
Bank x
READ
t
4
IS
Col n
T3
2
t
t
IH
LZ (MIN)
CL = 2
69
NOP
T4
t
1
RPRE
t
LZ (MIN)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RPRE
One bank
All banks
Bank x
PRE
T5
t
3
DO
t
DQSCK (MIN)
n
DQSCK (MAX)
512Mb: x4, x8, x16 DDR SDRAM
5
t
AC (MIN)
DO
t
n
AC (MAX)
T5n
t
RP
NOP
t
RAS (MIN) is met.
T6
1
Transitioning Data
t
HZ (MAX)
T6n
t
RPST
©2000 Micron Technology, Inc. All rights reserved.
t
RPST
NOP
T7
1
Operations
Bank x
Don’t Care
Row
Row
ACT
T8