IS42S32160B-7TL ISSI, Integrated Silicon Solution Inc, IS42S32160B-7TL Datasheet - Page 17
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IS42S32160B-7TL
Manufacturer Part Number
IS42S32160B-7TL
Description
IC SDRAM 512MBIT 143MHZ 86TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Specifications of IS42S32160B-7TL
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (16M x 32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOPII
Organization
16Mx32
Density
512Mb
Address Bus
15b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S32160B-7TLI
Manufacturer:
ISSI
Quantity:
1 000
IS42S32160B
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
03/27/08
Column Address
•
The Burst Type can be one of two modes,Interleave Mode or Sequential Mode.
A3
0
1
—Addressing Sequence of Sequential Mode
•
A column access is started in the input column address and is performed by inverting the address
bits in the sequence shown in the following table.
•
This field specifies the number of clock cycles from the assertion of the Read command to the first
read data.The minimum whole value of CAS#Latency depends on the frequency of CLK.The
minimum whole value satisfying the following formula must be programmed into this field.
t
Data n
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
CAC
Burst Length
(min)<=CAS#Latency X t
A6
0
0
0
0
1
Data n
Burst Type Field (A3)
Burst Type
Sequential
Interleave
An internal column address is performed by increasing the address from the column address which is input to the
device.The internal column address is varied by the Burst Length as shown in the following table.When the value
of column address,(n +m),in the table is larger than 255,only the least significant 8 bits are effective.
Addressing Sequence of Interleave Mode
CAS#Latency Field (A6~A4)
A5
0
0
1
1
X
A8
A8
A8
A8
A8
A8
A8
A8
A4
0
1
0
1
X
Full Page: Column address is repeated until terminated.
0
n
A7
A7
A7
A7
A7
A7
A7
A7
4 words:
2 words:
8 words:
Reserved
Reserved
2 clocks
3 clocks
Reserved
n+1
CAS#Latency
1
CK
A6
A6
A6
A6
A6
A6
A6
A6
n+2
2
Column Address
n+3
A5
A5
A5
A5
A5
A5
A5
A5
3
n+4
4
A4
A4
A4
A4
A4
A4
A4
A4
n+5
5
A3
A3
A3
A3
A3
A3
A3
A3
n+6
6
A2
A2
A2
A2
A2#
A2#
A2#
A2#
n+7
7
-
-
A1
A1
A1#
A1#
A1
A1
A1#
A1#
n+255
255
A0
A0#
A0
A0#
A0
A0#
A0
A0#
256
n
words
257
n+1
4
Burst Length
-
-
words
8
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