IS42S32160B-7TL ISSI, Integrated Silicon Solution Inc, IS42S32160B-7TL Datasheet - Page 7
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IS42S32160B-7TL
Manufacturer Part Number
IS42S32160B-7TL
Description
IC SDRAM 512MBIT 143MHZ 86TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Specifications of IS42S32160B-7TL
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (16M x 32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOPII
Organization
16Mx32
Density
512Mb
Address Bus
15b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S32160B-7TLI
Manufacturer:
ISSI
Quantity:
1 000
I
Commands
IS42S32160B
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
03/27/08
2
1
BankPrecharge command
(RAS#=”L”,CAS#=”H”,WE#=”L”,BS =Bank,A10 =”L”)
The BankPrecharge command precharges the bank disignated by BS0,1 signal.The
precharged bank is switched from the active state to the idle state.This command can be asserted anytime after
tRAS(min.)is satisfied from the BankActivate command in the desired bank.The maximum time any bank can be
active is specified by tRAS(max.).Therefore,the precharge function must be performed in any active bank within
tRAS(max.).At the end of precharge,the precharged bank is still in the idle state and is ready to be activated again.
ADDRESS
C O M M A N D
CLK
(RAS#=”L”,CAS#=”H”,WE#=”H”,BS =Bank,A0-A12 =Row Address)
The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal.By latching the
row address on A0 to A12 at the time of this command,the selected row access is initiated.The read or write
operation in the same bank can occur after a time delay of tRCD(min.)from the time of bank activation.A
subsequent BankActivate command to a different row in the same bank can only be issued after the previous
active row has been precharged (refer to the following figure).The minimum time interval between successive
BankActivate commands to the same bank is defined by tRC(min.).The SDRAM has four internal banks on the
same chip and shares part of the internal circuitry to reduce chip area;therefore it restricts the back-to-back
activation of the four banks.tRRD(min.)specifies the minimum time required between activating different banks.
After this command is used,the Write command and the Block Write command perform the no mask write
operation.
BankActivate
:"H" or "L"
Row Addr.
Activate
Bank A
Bank A
T0
RAS# - CAS# delay (
T1
NOP
Bank
T2
NOP
t
RCD
)
AutoPrecharge
Col Addr.
T3
R/W A with
Bank A
RAS# Cycle time (
..............
..............
..............
t
RC
)
Auto Precharge
Row Addr.
Tn+3
Begin
Activate
Bank B
Bank B
RAS#- RAS# delay time (
Tn+4
NOP
Tn+5
NOP
t
RRD
)
Row Addr.
I
Activate
Bank A
Bank A
Tn+6
®
7